| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR MIT |
| 2 | // |
| 3 | // Copyright 2016 Freescale Semiconductor, Inc. |
| 4 | |
| 5 | /dts-v1/; |
| 6 | |
| 7 | #include "imx6qp.dtsi" |
| 8 | #include "imx6qdl-sabreauto.dtsi" |
| 9 | |
| 10 | / { |
| 11 | model = "Freescale i.MX6 Quad Plus SABRE Automotive Board"; |
| 12 | compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp"; |
| 13 | }; |
| 14 | |
| 15 | &i2c2 { |
| 16 | max7322: gpio@68 { |
| 17 | compatible = "maxim,max7322"; |
| 18 | reg = <0x68>; |
| 19 | gpio-controller; |
| 20 | #gpio-cells = <2>; |
| 21 | }; |
| 22 | }; |
| 23 | |
| 24 | &iomuxc { |
| 25 | imx6qdl-sabreauto { |
| 26 | pinctrl_enet: enetgrp { |
| 27 | fsl,pins = < |
| 28 | MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 |
| 29 | MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 |
| 30 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018 |
| 31 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018 |
| 32 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018 |
| 33 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018 |
| 34 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018 |
| 35 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018 |
| 36 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018 |
| 37 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018 |
| 38 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018 |
| 39 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018 |
| 40 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018 |
| 41 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018 |
| 42 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 |
| 43 | MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 |
| 44 | >; |
| 45 | }; |
| 46 | }; |
| 47 | }; |
| 48 | |
| 49 | &pcie { |
| 50 | reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>; |
| 51 | status = "okay"; |
| 52 | }; |
| 53 | |
| 54 | &sata { |
| 55 | status = "okay"; |
| 56 | }; |
| 57 | |
| 58 | &vgen3_reg { |
| 59 | regulator-always-on; |
| 60 | }; |