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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / nxp / imx / imx6qdl-var-som.dtsi
blob: a1ea33c4eeb75c549777181c5f98fe9fb8e3232e [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Support for Variscite VAR-SOM-MX6 Module
4 *
5 * Copyright 2011 Linaro Ltd.
6 * Copyright 2012 Freescale Semiconductor, Inc.
7 * Copyright (C) 2014-2016 Variscite, Ltd.
8 * Author: Donio Ron <ron.d@variscite.com>
9 * Copyright 2022 Bootlin
10 */
11
12/dts-v1/;
13
14#include "imx6q.dtsi"
15#include <dt-bindings/clock/imx6qdl-clock.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/sound/fsl-imx-audmux.h>
18
19/ {
20 model = "Variscite VAR-SOM-MX6 module";
21 compatible = "variscite,var-som-imx6q", "fsl,imx6q";
22
23 chosen {
24 stdout-path = &uart1;
25 };
26
27 memory@10000000 {
28 device_type = "memory";
29 reg = <0x10000000 0x40000000>;
30 };
31
32 reg_usb_otg_vbus: regulator-usb-otg-vbus {
33 compatible = "regulator-fixed";
34 regulator-name = "usb_otg_vbus";
35 regulator-min-microvolt = <5000000>;
36 regulator-max-microvolt = <5000000>;
37 };
38
39 reg_usb_h1_vbus: regulator-usb-h1-vbud {
40 compatible = "regulator-fixed";
41 regulator-name = "usb_h1_vbus";
42 regulator-min-microvolt = <5000000>;
43 regulator-max-microvolt = <5000000>;
44 };
45
46 reg_1p8v: regulator-1p8v {
47 compatible = "regulator-fixed";
48 regulator-name = "1P8V";
49 regulator-min-microvolt = <1800000>;
50 regulator-max-microvolt = <1800000>;
51 regulator-always-on;
52 };
53
54 reg_3p3v: regulator-3p3v {
55 compatible = "regulator-fixed";
56 regulator-name = "3P3V";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 regulator-always-on;
60 };
61
62 reg_wl18xx_vmmc: regulator-wl18xx {
63 compatible = "regulator-fixed";
64 regulator-name = "vwl1807";
65 regulator-min-microvolt = <1800000>;
66 regulator-max-microvolt = <1800000>;
67 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
68 enable-active-high;
69 startup-delay-us = <70000>;
70 };
71
72 sound: sound {
73 compatible = "simple-audio-card";
74 simple-audio-card,name = "var-som-audio";
75 simple-audio-card,format = "i2s";
76 simple-audio-card,bitclock-master = <&sound_codec>;
77 simple-audio-card,frame-master = <&sound_codec>;
78 simple-audio-card,widgets = "Headphone", "Headphone Jack",
79 "Line", "Line In", "Microphone", "Mic Jack";
80 simple-audio-card,routing = "Headphone Jack", "HPLOUT",
81 "Headphone Jack", "HPROUT",
82 "LINE1L", "Line In",
83 "LINE1R", "Line In";
84
85 sound_cpu: simple-audio-card,cpu {
86 sound-dai = <&ssi2>;
87 };
88
89 sound_codec: simple-audio-card,codec {
90 sound-dai = <&tlv320aic3106>;
91 clocks = <&clks IMX6QDL_CLK_CKO>;
92 };
93 };
94
95 rfkill {
96 compatible = "rfkill-gpio";
97 name = "rfkill";
98 radio-type = "bluetooth";
99 shutdown-gpios = <&gpio6 18 GPIO_ACTIVE_HIGH>;
100 };
101};
102
103&audmux {
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_audmux>;
106 status = "okay";
107
108 mux-ssi2 {
109 fsl,audmux-port = <1>;
110 fsl,port-config = <
111 (IMX_AUDMUX_V2_PTCR_SYN |
112 IMX_AUDMUX_V2_PTCR_TFSDIR |
113 IMX_AUDMUX_V2_PTCR_TFSEL(2) |
114 IMX_AUDMUX_V2_PTCR_TCLKDIR |
115 IMX_AUDMUX_V2_PTCR_TCSEL(2))
116 IMX_AUDMUX_V2_PDCR_RXDSEL(2)
117 >;
118 };
119
120 mux-aud3 {
121 fsl,audmux-port = <2>;
122 fsl,port-config = <
123 IMX_AUDMUX_V2_PTCR_SYN
124 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
125 >;
126 };
127};
128
129&ecspi3 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_ecspi3>;
132 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
133 status = "okay";
134};
135
136&fec {
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_enet>;
139 phy-mode = "rgmii";
140 phy-handle = <&rgmii_phy>;
141 status = "okay";
142
143 mdio {
144 #address-cells = <1>;
145 #size-cells = <0>;
146
147 rgmii_phy: ethernet-phy@7 {
148 reg = <7>;
149 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
150 reset-assert-us = <10000>;
151 };
152 };
153};
154
155&gpmi {
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_gpmi_nand>;
158 status = "okay";
159};
160
161&i2c2 {
162 clock-frequency = <100000>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_i2c2>;
165 status = "okay";
166
167 pmic@8 {
168 compatible = "fsl,pfuze100";
169 reg = <0x08>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_pmic>;
172
173 regulators {
174 sw1a_reg: sw1ab {
175 regulator-min-microvolt = <300000>;
176 regulator-max-microvolt = <1875000>;
177 regulator-boot-on;
178 regulator-always-on;
179 regulator-ramp-delay = <6250>;
180 };
181
182 sw1c_reg: sw1c {
183 regulator-min-microvolt = <300000>;
184 regulator-max-microvolt = <1875000>;
185 regulator-boot-on;
186 regulator-always-on;
187 regulator-ramp-delay = <6250>;
188 };
189
190 sw2_reg: sw2 {
191 regulator-min-microvolt = <800000>;
192 regulator-max-microvolt = <3300000>;
193 regulator-boot-on;
194 regulator-always-on;
195 };
196
197 sw3a_reg: sw3a {
198 regulator-min-microvolt = <800000>;
199 regulator-max-microvolt = <3950000>;
200 regulator-boot-on;
201 regulator-always-on;
202 };
203
204 sw3b_reg: sw3b {
205 regulator-min-microvolt = <800000>;
206 regulator-max-microvolt = <3950000>;
207 regulator-boot-on;
208 regulator-always-on;
209 };
210
211 sw4_reg: sw4 {
212 regulator-min-microvolt = <800000>;
213 regulator-max-microvolt = <3950000>;
214 };
215
216 snvs_reg: vsnvs {
217 regulator-min-microvolt = <1200000>;
218 regulator-max-microvolt = <3000000>;
219 regulator-boot-on;
220 regulator-always-on;
221 };
222
223 vref_reg: vrefddr {
224 regulator-boot-on;
225 regulator-always-on;
226 };
227
228 vgen1_reg: vgen1 {
229 regulator-min-microvolt = <800000>;
230 regulator-max-microvolt = <1550000>;
231 };
232
233 vgen2_reg: vgen2 {
234 regulator-min-microvolt = <800000>;
235 regulator-max-microvolt = <1550000>;
236 };
237
238 vgen3_reg: vgen3 {
239 regulator-min-microvolt = <1800000>;
240 regulator-max-microvolt = <3300000>;
241 regulator-always-on;
242 regulator-boot-on;
243 };
244
245 vgen4_reg: vgen4 {
246 regulator-min-microvolt = <1800000>;
247 regulator-max-microvolt = <3300000>;
248 regulator-always-on;
249 regulator-boot-on;
250 };
251
252 vgen5_reg: vgen5 {
253 regulator-min-microvolt = <1800000>;
254 regulator-max-microvolt = <3300000>;
255 regulator-always-on;
256 regulator-boot-on;
257 };
258
259 vgen6_reg: vgen6 {
260 regulator-min-microvolt = <2800000>;
261 regulator-max-microvolt = <2800000>;
262 regulator-always-on;
263 regulator-boot-on;
264 };
265 };
266 };
267
268 tlv320aic3106: audio-codec@1b {
269 compatible = "ti,tlv320aic3106";
270 reg = <0x1b>;
271 #sound-dai-cells = <0>;
272 DRVDD-supply = <&reg_3p3v>;
273 AVDD-supply = <&reg_3p3v>;
274 IOVDD-supply = <&reg_3p3v>;
275 DVDD-supply = <&reg_1p8v>;
276 ai3x-ocmv = <0>;
277 reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
278 ai3x-gpio-func = <
279 0 /* AIC3X_GPIO1_FUNC_DISABLED */
280 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */
281 >;
282 };
283};
284
285&iomuxc {
286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_hog>;
288
289 pinctrl_audmux: audmuxgrp {
290 fsl,pins = <
291 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
292 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
293 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
294 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
295 /* Audio Clock */
296 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
297 >;
298 };
299
300 pinctrl_bt: btgrp {
301 fsl,pins = <
302 /* Bluetooth/wifi enable */
303 MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b1
304 /* Wifi Slow Clock */
305 MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x000b0
306 >;
307 };
308
309 pinctrl_ecspi3: ecspi3grp {
310 fsl,pins = <
311 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
312 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
313 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
314 >;
315 };
316
317 pinctrl_enet: enetgrp {
318 fsl,pins = <
319 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
320 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
321 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
322 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
323 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
324 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
325 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
326 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
327 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
328 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
329 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
330 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
331 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
332 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
333 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
334 >;
335 };
336
337 pinctrl_enet_irq: enetirqgrp {
338 fsl,pins = <
339 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
340 >;
341 };
342
343 pinctrl_gpmi_nand: gpminandgrp {
344 fsl,pins = <
345 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
346 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
347 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
348 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
349 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb0b1
350 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
351 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
352 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
353 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
354 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
355 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
356 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
357 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
358 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
359 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
360 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
361 >;
362 };
363
364 pinctrl_hog: hoggrp {
365 fsl,pins = <
366 /* CTW6120 IRQ */
367 MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0xb0b1
368 /* SDMMC2 CD/WP */
369 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
370 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
371 >;
372 };
373
374 pinctrl_i2c1: i2c1grp {
375 fsl,pins = <
376 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
377 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
378 >;
379 };
380
381 pinctrl_i2c2: i2c2grp {
382 fsl,pins = <
383 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
384 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
385 >;
386 };
387
388 pinctrl_i2c3: i2c3grp {
389 fsl,pins = <
390 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
391 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
392 >;
393 };
394
395 pinctrl_pmic: pmicgrp {
396 fsl,pins = <
397 /* PMIC INT */
398 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
399 >;
400 };
401
402 pinctrl_pwm2: pwm2grp {
403 fsl,pins = <
404 MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
405 >;
406 };
407
408 pinctrl_uart1: uart1grp {
409 fsl,pins = <
410 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
411 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
412 >;
413 };
414
415 pinctrl_uart2: uart2grp {
416 fsl,pins = <
417 MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
418 MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
419 MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
420 MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
421 >;
422 };
423
424 pinctrl_usdhc3: usdhc3grp {
425 fsl,pins = <
426 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17069
427 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10069
428 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17069
429 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17069
430 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17069
431 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17069
432 /* WL_EN */
433 MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x13059
434 /* WL_IRQ */
435 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059
436 >;
437 };
438
439 pinctrl_usdhc3_100mhz: usdhc3grp100mhzgrp {
440 fsl,pins = <
441 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9
442 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9
443 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9
444 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9
445 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
446 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
447 /* WL_EN */
448 MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x130B9
449 /* WL_IRQ */
450 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x130B9
451 >;
452 };
453
454 pinctrl_usdhc3_200mhz: usdhc3grp200mhzgrp {
455 fsl,pins = <
456 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
457 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
458 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
459 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
460 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
461 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
462 /* WL_EN */
463 MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x130F9
464 /* WL_IRQ */
465 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x130F9
466 >;
467 };
468};
469
470&pwm2 {
471 pinctrl-names = "default";
472 pinctrl-0 = <&pinctrl_pwm2>;
473 status = "okay";
474};
475
476&reg_arm {
477 vin-supply = <&sw1a_reg>;
478};
479
480&reg_pu {
481 vin-supply = <&sw1c_reg>;
482};
483
484&reg_soc {
485 vin-supply = <&sw1c_reg>;
486};
487
488&reg_vdd1p1 {
489 vin-supply = <&vgen5_reg>;
490};
491
492&reg_vdd2p5 {
493 vin-supply = <&vgen5_reg>;
494};
495
496&snvs_poweroff {
497 status = "okay";
498};
499
500&ssi2 {
501 status = "okay";
502};
503
504&uart1 {
505 pinctrl-names = "default";
506 pinctrl-0 = <&pinctrl_uart1>;
507 status = "okay";
508};
509
510&uart2 {
511 pinctrl-names = "default";
512 pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt>;
513 uart-has-rtscts;
514 status = "okay";
515};
516
517&usbh1 {
518 vbus-supply = <&reg_usb_h1_vbus>;
519 status = "okay";
520};
521
522&usbotg {
523 vbus-supply = <&reg_usb_otg_vbus>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&pinctrl_usbotg_var>;
526 disable-over-current;
527 dr_mode = "host";
528 status = "okay";
529};
530
531&usbphy1 {
532 fsl,tx-d-cal = <0x5>;
533};
534
535&usbphy2 {
536 fsl,tx-d-cal = <0x5>;
537};
538
539&usdhc1 {
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_usdhc1>;
542 non-removable;
543 keep-power-in-suspend;
544 status = "okay";
545};
546
547&usdhc3 {
548 pinctrl-names = "default", "state_100mhz", "state_200mhz";
549 pinctrl-0 = <&pinctrl_usdhc3>;
550 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
551 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
552 bus-width = <4>;
553 vmmc-supply = <&reg_wl18xx_vmmc>;
554 non-removable;
555 wakeup-source;
556 keep-power-in-suspend;
557 cap-power-off-card;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 status = "okay";
561
562 wifi: wifi@2 {
563 compatible = "ti,wl1835";
564 reg = <2>;
565 interrupt-parent = <&gpio6>;
566 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
567 ref-clock-frequency = <38400000>;
568 };
569};