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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / nxp / imx / imx6qdl-ts4900.dtsi
blob: f88da757edda5a172d82745d5b5c1abb935b7d79 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1/*
2 * Copyright 2015 Technologic Systems
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42#include <dt-bindings/gpio/gpio.h>
43#include <dt-bindings/interrupt-controller/irq.h>
44
45/ {
46 aliases {
47 ethernet0 = &fec;
48 };
49
50 leds {
51 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_leds1>;
53 compatible = "gpio-leds";
54
55 green-led {
56 label = "green-led";
57 gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
58 default-state = "on";
59 };
60
61 red-led {
62 label = "red-led";
63 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
64 default-state = "off";
65 };
66 };
67
68 reg_3p3v: regulator-3p3v {
69 compatible = "regulator-fixed";
70 regulator-name = "3p3v";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 };
74
75 reg_usb_otg_vbus: regulator-usb-otg-vbus {
76 compatible = "regulator-fixed";
77 regulator-name = "usb_otg_vbus";
78 regulator-min-microvolt = <5000000>;
79 regulator-max-microvolt = <5000000>;
80 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
81 enable-active-high;
82 };
83};
84
85&can1 {
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_flexcan1>;
88 status = "okay";
89};
90
91&can2 {
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_flexcan2>;
94 status = "okay";
95};
96
97&ecspi1 {
98 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_ecspi1>;
101 status = "okay";
102
103 n25q064: flash@0 {
104 compatible = "micron,n25q064", "jedec,spi-nor";
105 reg = <0>;
106 spi-max-frequency = <20000000>;
107 };
108};
109
110&ecspi2 {
111 cs-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_ecspi2>;
114 status = "okay";
115};
116
117&fec {
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_enet>;
120 phy-mode = "rgmii";
121 status = "okay";
122};
123
124&i2c1 {
125 clock-frequency = <100000>;
126 pinctrl-names = "default", "gpio";
127 pinctrl-0 = <&pinctrl_i2c1>;
128 pinctrl-1 = <&pinctrl_i2c1_gpio>;
129 scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
130 sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
131 status = "okay";
132
133 isl12022: rtc@6f {
134 compatible = "isil,isl12022";
135 reg = <0x6f>;
136 };
137
138 gpio8: gpio@28 {
139 compatible = "technologic,ts4900-gpio";
140 reg = <0x28>;
141 #gpio-cells = <2>;
142 gpio-controller;
143 ngpio = <32>;
144 };
145};
146
147&i2c2 {
148 clock-frequency = <100000>;
149 pinctrl-names = "default", "gpio";
150 pinctrl-0 = <&pinctrl_i2c2>;
151 pinctrl-1 = <&pinctrl_i2c2_gpio>;
152 scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
153 sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
154 status = "okay";
155};
156
157&iomuxc {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_hog>;
160
161 pinctrl_ecspi1: ecspi1grp {
162 fsl,pins = <
163 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
164 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
165 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
166 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard flash CS1# */
167 >;
168 };
169
170 pinctrl_ecspi2: ecspi2grp {
171 fsl,pins = <
172 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
173 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
174 MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
175 MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 /* Offboard CS0# */
176 MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x100b1 /* FPGA CS1# */
177 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 /* FPGA_RESET# */
178 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* FPGA_DONE */
179 MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */
180 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 /* FPGA_IRQ */
181 >;
182 };
183
184 pinctrl_enet: enetgrp {
185 fsl,pins = <
186 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
187 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
188 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
189 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
190 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
191 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
192 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
193 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
194 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
195 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
196 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
197 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
198 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
199 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
200 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001b0a8
201 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1
202 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b1 /* ETH_PHY_RESET */
203 >;
204 };
205
206 pinctrl_flexcan1: flexcan1grp {
207 fsl,pins = <
208 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
209 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
210 >;
211 };
212
213 pinctrl_flexcan2: flexcan2grp {
214 fsl,pins = <
215 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1
216 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1
217 >;
218 };
219
220 pinctrl_hog: hoggrp {
221 fsl,pins = <
222 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 /* OFF_BD_RESET# */
223 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 /* EN_USB_5V# */
224 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b1 /* EN_LCD_3.3V */
225 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */
226 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 /* DIO_1 */
227 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b1 /* DIO_2 */
228 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b1 /* DIO_3 */
229 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b1 /* DIO_4 */
230 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 /* DIO_5 */
231 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 /* DIO_7 */
232 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b1 /* DIO_8 */
233 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b1 /* DIO_9 */
234 MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* DIO_0 */
235 MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b1 /* DIO_6 */
236 MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b1 /* CPU_DIO_A */
237 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b1 /* DIO_2 */
238 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 /* CPU_DIO_B */
239 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 /* BUS_ALE# */
240 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 /* DIO_15 */
241 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 /* BUS_DIR */
242 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 /* BUS_CS# */
243 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* DIO_14 */
244 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b1 /* DIO_16 */
245 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b1 /* DIO_12 */
246 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 /* DIO_18 */
247 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b1 /* DIO_19 */
248 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 /* DIO_20 */
249 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b1 /* BUS_BHE# */
250 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 /* DIO_13 */
251 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 /* EIM_WAIT# */
252 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b1 /* DIO_10 */
253 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 /* MUX_AD_00 */
254 MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 /* MUX_AD_01 */
255 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 /* MUX_AD_02 */
256 MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 /* MUX_AD_03 */
257 MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 /* MUX_AD_04 */
258 MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 /* MUX_AD_05 */
259 MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 /* MUX_AD_06 */
260 MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 /* MUX_AD_07 */
261 MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 /* MUX_AD_08 */
262 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 /* MUX_AD_09 */
263 MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 /* MUX_AD_10 */
264 MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 /* MUX_AD_11 */
265 MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 /* MUX_AD_12 */
266 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 /* MUX_AD_13 */
267 MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 /* MUX_AD_14 */
268 MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 /* MUX_AD_15 */
269 MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 /* LCD_CLK */
270 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b1 /* DE */
271 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b1 /* Hsync */
272 MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b1 /* Vsync */
273 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b1
274 MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b1
275 MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x1b0b1
276 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b1
277 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1
278 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b1
279 MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b1
280 MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b1
281 MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x1b0b1
282 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b1
283 MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b1
284 MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b1
285 MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b1
286 MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1
287 MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1
288 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1
289 MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1
290 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1
291 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b1
292 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1
293 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b1
294 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1
295 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b1
296 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1
297 >;
298 };
299
300 pinctrl_i2c1: i2c1grp {
301 fsl,pins = <
302 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
303 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
304 >;
305 };
306
307 pinctrl_i2c1_gpio: i2c1gpiogrp {
308 fsl,pins = <
309 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
310 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
311 >;
312 };
313
314 pinctrl_i2c2: i2c2grp {
315 fsl,pins = <
316 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
317 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
318 >;
319 };
320
321 pinctrl_i2c2_gpio: i2c2gpiogrp {
322 fsl,pins = <
323 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
324 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
325 >;
326 };
327
328 pinctrl_leds1: leds1grp {
329 fsl,pins = <
330 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /* RED_LED# */
331 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 /* GREEN_LED# */
332 >;
333 };
334
335 pinctrl_uart1: uart1grp {
336 fsl,pins = <
337 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
338 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
339 >;
340 };
341
342 pinctrl_uart2: uart2grp {
343 fsl,pins = <
344 MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1
345 MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1
346 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
347 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
348 >;
349 };
350
351 pinctrl_uart3: uart3grp {
352 fsl,pins = <
353 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
354 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
355 >;
356 };
357
358 pinctrl_uart4: uart4grp {
359 fsl,pins = <
360 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
361 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
362 >;
363 };
364
365 pinctrl_uart5: uart5grp {
366 fsl,pins = <
367 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
368 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
369 >;
370 };
371
372 pinctrl_usbotg: usbotggrp {
373 fsl,pins = <
374 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
375 >;
376 };
377
378 pinctrl_usdhc1: usdhc1grp {
379 fsl,pins = <
380 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
381 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
382 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
383 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
384 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
385 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
386 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */
387 >;
388 };
389
390 pinctrl_usdhc2: usdhc2grp {
391 fsl,pins = <
392 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
393 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
394 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
395 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
396 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
397 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
398 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b1 /* EN_SD_POWER# */
399 >;
400 };
401
402 pinctrl_usdhc3: usdhc3grp {
403 fsl,pins = <
404 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
405 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
406 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
407 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
408 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
409 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
410 >;
411 };
412};
413
414&pcie {
415 status = "okay";
416};
417
418&uart1 {
419 pinctrl-names = "default";
420 pinctrl-0 = <&pinctrl_uart1>;
421 status = "okay";
422};
423
424&uart2 {
425 pinctrl-names = "default";
426 pinctrl-0 = <&pinctrl_uart2>;
427 uart-has-rtscts;
428 status = "okay";
429};
430
431&uart3 {
432 pinctrl-names = "default";
433 pinctrl-0 = <&pinctrl_uart3>;
434 status = "okay";
435};
436
437&uart4 {
438 pinctrl-names = "default";
439 pinctrl-0 = <&pinctrl_uart4>;
440 status = "okay";
441};
442
443&uart5 {
444 pinctrl-names = "default";
445 pinctrl-0 = <&pinctrl_uart5>;
446 status = "okay";
447};
448
449&usbh1 {
450 status = "okay";
451};
452
453&usbotg {
454 vbus-supply = <&reg_usb_otg_vbus>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&pinctrl_usbotg>;
457 disable-over-current;
458 status = "okay";
459};
460
461/* SD */
462&usdhc2 {
463 pinctrl-names = "default";
464 pinctrl-0 = <&pinctrl_usdhc2>;
465 vmmc-supply = <&reg_3p3v>;
466 bus-width = <4>;
467 fsl,wp-controller;
468 status = "okay";
469};
470
471/* eMMC */
472&usdhc3 {
473 pinctrl-names = "default";
474 pinctrl-0 = <&pinctrl_usdhc3>;
475 vmmc-supply = <&reg_3p3v>;
476 bus-width = <4>;
477 non-removable;
478 status = "okay";
479};