Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / nxp / imx / imx6qdl-rex.dtsi
blob: eba698d04243a688b7648b3aa41c71f2021315cb [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2014 FEDEVEL, Inc.
4 *
5 * Author: Robert Nelson <robertcnelson@gmail.com>
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10
11/ {
12 chosen {
13 stdout-path = &uart1;
14 };
15
16 reg_3p3v: regulator-3p3v {
17 compatible = "regulator-fixed";
18 regulator-name = "3P3V";
19 regulator-min-microvolt = <3300000>;
20 regulator-max-microvolt = <3300000>;
21 regulator-always-on;
22 };
23
24 reg_usbh1_vbus: regulator-usbh1-vbus {
25 compatible = "regulator-fixed";
26 pinctrl-names = "default";
27 regulator-name = "usbh1_vbus";
28 regulator-min-microvolt = <5000000>;
29 regulator-max-microvolt = <5000000>;
30 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
31 enable-active-high;
32 };
33
34 reg_usb_otg_vbus: regulator-otg-vbus {
35 compatible = "regulator-fixed";
36 pinctrl-names = "default";
37 regulator-name = "usb_otg_vbus";
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
40 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
41 enable-active-high;
42 };
43
44 leds {
45 compatible = "gpio-leds";
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_led>;
48
49 led0: led-usr {
50 label = "usr";
51 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
52 default-state = "off";
53 linux,default-trigger = "heartbeat";
54 };
55 };
56
57 sound {
58 compatible = "fsl,imx6-rex-sgtl5000",
59 "fsl,imx-audio-sgtl5000";
60 model = "imx6-rex-sgtl5000";
61 ssi-controller = <&ssi1>;
62 audio-codec = <&codec>;
63 audio-routing =
64 "MIC_IN", "Mic Jack",
65 "Mic Jack", "Mic Bias",
66 "Headphone Jack", "HP_OUT";
67 mux-int-port = <1>;
68 mux-ext-port = <3>;
69 };
70};
71
72&audmux {
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_audmux>;
75 status = "okay";
76};
77
78&ecspi2 {
79 cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_ecspi2>;
82 status = "okay";
83};
84
85&ecspi3 {
86 cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_ecspi3>;
89 status = "okay";
90};
91
92&fec {
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_enet>;
95 phy-mode = "rgmii";
96 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
97 status = "okay";
98};
99
100&hdmi {
101 ddc-i2c-bus = <&i2c2>;
102 status = "okay";
103};
104
105&i2c1 {
106 clock-frequency = <100000>;
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_i2c1>;
109 status = "okay";
110
111 codec: sgtl5000@a {
112 compatible = "fsl,sgtl5000";
113 reg = <0x0a>;
114 #sound-dai-cells = <0>;
115 clocks = <&clks IMX6QDL_CLK_CKO>;
116 VDDA-supply = <&reg_3p3v>;
117 VDDIO-supply = <&reg_3p3v>;
118 };
119};
120
121&i2c2 {
122 clock-frequency = <100000>;
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_i2c2>;
125 status = "okay";
126
127 pca9535: gpio-expander@27 {
128 compatible = "nxp,pca9535";
129 reg = <0x27>;
130 gpio-controller;
131 #gpio-cells = <2>;
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_pca9535>;
134 interrupt-parent = <&gpio6>;
135 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
136 interrupt-controller;
137 #interrupt-cells = <2>;
138 };
139
140 eeprom@57 {
141 compatible = "atmel,24c02";
142 reg = <0x57>;
143 };
144};
145
146&i2c3 {
147 clock-frequency = <100000>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_i2c3>;
150 status = "okay";
151};
152
153&iomuxc {
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_hog>;
156
157 imx6qdl-rex {
158 pinctrl_hog: hoggrp {
159 fsl,pins = <
160 /* SGTL5000 sys_mclk */
161 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
162 >;
163 };
164
165 pinctrl_audmux: audmuxgrp {
166 fsl,pins = <
167 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
168 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
169 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
170 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
171 >;
172 };
173
174 pinctrl_ecspi2: ecspi2grp {
175 fsl,pins = <
176 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
177 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
178 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
179 /* CS */
180 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1
181 >;
182 };
183
184 pinctrl_ecspi3: ecspi3grp {
185 fsl,pins = <
186 MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1
187 MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
188 MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1
189 /* CS */
190 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1
191 >;
192 };
193
194 pinctrl_enet: enetgrp {
195 fsl,pins = <
196 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
197 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
198 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
199 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
200 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
201 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
202 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
203 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
204 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
205 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
206 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
207 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
208 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
209 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
210 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
211 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
212 /* Phy reset */
213 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
214 >;
215 };
216
217 pinctrl_i2c1: i2c1grp {
218 fsl,pins = <
219 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
220 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
221 >;
222 };
223
224 pinctrl_i2c2: i2c2grp {
225 fsl,pins = <
226 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
227 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
228 >;
229 };
230
231 pinctrl_i2c3: i2c3grp {
232 fsl,pins = <
233 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
234 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
235 >;
236 };
237
238 pinctrl_led: ledgrp {
239 fsl,pins = <
240 /* user led */
241 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
242 >;
243 };
244
245 pinctrl_pca9535: pca9535grp {
246 fsl,pins = <
247 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x17059
248 >;
249 };
250
251 pinctrl_uart1: uart1grp {
252 fsl,pins = <
253 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
254 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
255 >;
256 };
257
258 pinctrl_uart2: uart2grp {
259 fsl,pins = <
260 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
261 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
262 >;
263 };
264
265 pinctrl_usbh1: usbh1grp {
266 fsl,pins = <
267 /* power enable, high active */
268 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0
269 >;
270 };
271
272 pinctrl_usbotg: usbotggrp {
273 fsl,pins = <
274 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
275 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
276 /* power enable, high active */
277 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0
278 >;
279 };
280
281 pinctrl_usdhc2: usdhc2grp {
282 fsl,pins = <
283 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
284 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
285 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
286 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
287 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
288 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
289 /* CD */
290 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
291 /* WP */
292 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0
293 >;
294 };
295
296 pinctrl_usdhc3: usdhc3grp {
297 fsl,pins = <
298 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
299 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
300 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
301 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
302 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
303 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
304 /* CD */
305 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
306 /* WP */
307 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0
308 >;
309 };
310 };
311};
312
313&ssi1 {
314 status = "okay";
315};
316
317&uart1 {
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_uart1>;
320 status = "okay";
321};
322
323&uart2 {
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_uart2>;
326 status = "okay";
327};
328
329&usbh1 {
330 vbus-supply = <&reg_usbh1_vbus>;
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_usbh1>;
333 status = "okay";
334};
335
336&usbotg {
337 vbus-supply = <&reg_usb_otg_vbus>;
338 pinctrl-names = "default";
339 pinctrl-0 = <&pinctrl_usbotg>;
340 status = "okay";
341};
342
343&usdhc2 {
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_usdhc2>;
346 bus-width = <4>;
347 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
348 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
349 status = "okay";
350};
351
352&usdhc3 {
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_usdhc3>;
355 bus-width = <4>;
356 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
357 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
358 status = "okay";
359};