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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / nxp / imx / imx6qdl-kontron-samx6i.dtsi
blob: 85aeebc9485dd31b63fdf418d140551682b0c270 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Copyright 2017 (C) Priit Laes <plaes@plaes.org>
4 * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de>
5 * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de>
6 *
7 * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru>
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/sound/fsl-imx-audmux.h>
12
13/ {
14 reg_1p0v_s0: regulator-1p0v-s0 {
15 compatible = "regulator-fixed";
16 regulator-name = "V_1V0_S0";
17 regulator-min-microvolt = <1000000>;
18 regulator-max-microvolt = <1000000>;
19 regulator-always-on;
20 regulator-boot-on;
21 vin-supply = <&reg_smarc_suppy>;
22 };
23
24 reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 {
25 compatible = "regulator-fixed";
26 regulator-name = "V_1V35_VCOREDIG_S5";
27 regulator-min-microvolt = <1350000>;
28 regulator-max-microvolt = <1350000>;
29 regulator-always-on;
30 regulator-boot-on;
31 vin-supply = <&reg_3p3v_s5>;
32 };
33
34 reg_1p8v_s5: regulator-1p8v-s5 {
35 compatible = "regulator-fixed";
36 regulator-name = "V_1V8_S5";
37 regulator-min-microvolt = <1800000>;
38 regulator-max-microvolt = <1800000>;
39 regulator-always-on;
40 regulator-boot-on;
41 vin-supply = <&reg_3p3v_s5>;
42 };
43
44 reg_3p3v_s0: regulator-3p3v-s0 {
45 compatible = "regulator-fixed";
46 regulator-name = "V_3V3_S0";
47 regulator-min-microvolt = <3300000>;
48 regulator-max-microvolt = <3300000>;
49 regulator-always-on;
50 regulator-boot-on;
51 vin-supply = <&reg_3p3v_s5>;
52 };
53
54 reg_3p3v_s5: regulator-3p3v-s5 {
55 compatible = "regulator-fixed";
56 regulator-name = "V_3V3_S5";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 regulator-always-on;
60 regulator-boot-on;
61 vin-supply = <&reg_smarc_suppy>;
62 };
63
64 reg_smarc_lcdbklt: regulator-smarc-lcdbklt {
65 compatible = "regulator-fixed";
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_lcdbklt_en>;
68 regulator-name = "LCD_BKLT_EN";
69 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <1800000>;
71 gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
72 enable-active-high;
73 };
74
75 reg_smarc_lcdvdd: regulator-smarc-lcdvdd {
76 compatible = "regulator-fixed";
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_lcdvdd_en>;
79 regulator-name = "LCD_VDD_EN";
80 regulator-min-microvolt = <1800000>;
81 regulator-max-microvolt = <1800000>;
82 gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
83 enable-active-high;
84 };
85
86 reg_smarc_rtc: regulator-smarc-rtc {
87 compatible = "regulator-fixed";
88 regulator-name = "V_IN_RTC_BATT";
89 regulator-min-microvolt = <3300000>;
90 regulator-max-microvolt = <3300000>;
91 regulator-always-on;
92 regulator-boot-on;
93 };
94
95 /* Module supply range can be 3.00V ... 5.25V */
96 reg_smarc_suppy: regulator-smarc-supply {
97 compatible = "regulator-fixed";
98 regulator-name = "V_IN_WIDE";
99 regulator-min-microvolt = <5000000>;
100 regulator-max-microvolt = <5000000>;
101 regulator-always-on;
102 regulator-boot-on;
103 };
104
105 lcd: lcd {
106 #address-cells = <1>;
107 #size-cells = <0>;
108 compatible = "fsl,imx-parallel-display";
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_lcd>;
111 status = "disabled";
112
113 port@0 {
114 reg = <0>;
115
116 lcd_in: endpoint {
117 };
118 };
119
120 port@1 {
121 reg = <1>;
122
123 lcd_out: endpoint {
124 };
125 };
126 };
127
128 lcd_backlight: lcd-backlight {
129 compatible = "pwm-backlight";
130 pwms = <&pwm4 0 5000000 0>;
131 pwm-names = "LCD_BKLT_PWM";
132
133 brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
134 default-brightness-level = <4>;
135
136 power-supply = <&reg_smarc_lcdbklt>;
137 status = "disabled";
138 };
139
140 i2c_intern: i2c-gpio-intern {
141 compatible = "i2c-gpio";
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_i2c_gpio_intern>;
144 sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
145 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
146 i2c-gpio,delay-us = <2>; /* ~100 kHz */
147 #address-cells = <1>;
148 #size-cells = <0>;
149 };
150
151 i2c_lcd: i2c-gpio-lcd {
152 compatible = "i2c-gpio";
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_i2c_gpio_lcd>;
155 sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
156 scl-gpios = <&gpio1 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
157 i2c-gpio,delay-us = <2>; /* ~100 kHz */
158 #address-cells = <1>;
159 #size-cells = <0>;
160 status = "disabled";
161 };
162
163 i2c_cam: i2c-gpio-cam {
164 compatible = "i2c-gpio";
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_i2c_gpio_cam>;
167 sda-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
168 scl-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
169 i2c-gpio,delay-us = <2>; /* ~100 kHz */
170 #address-cells = <1>;
171 #size-cells = <0>;
172 status = "disabled";
173 };
174};
175
176/* I2S0, I2S1 */
177&audmux {
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_audmux>;
180
181 audmux_ssi1 {
182 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
183 fsl,port-config = <
184 (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) |
185 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT3) |
186 IMX_AUDMUX_V2_PTCR_SYN |
187 IMX_AUDMUX_V2_PTCR_TFSDIR |
188 IMX_AUDMUX_V2_PTCR_TCLKDIR)
189 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT3)
190 >;
191 };
192
193 audmux_adu3 {
194 fsl,audmux-port = <MX51_AUDMUX_PORT3>;
195 fsl,port-config = <
196 IMX_AUDMUX_V2_PTCR_SYN
197 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
198 >;
199 };
200
201 audmux_ssi2 {
202 fsl,audmux-port = <MX51_AUDMUX_PORT2_SSI1>;
203 fsl,port-config = <
204 (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
205 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
206 IMX_AUDMUX_V2_PTCR_SYN |
207 IMX_AUDMUX_V2_PTCR_TFSDIR |
208 IMX_AUDMUX_V2_PTCR_TCLKDIR)
209 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
210 >;
211 };
212
213 audmux_adu4 {
214 fsl,audmux-port = <MX51_AUDMUX_PORT4>;
215 fsl,port-config = <
216 IMX_AUDMUX_V2_PTCR_SYN
217 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT2_SSI1)
218 >;
219 };
220};
221
222/* CAN0 */
223&can1 {
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_flexcan1>;
226};
227
228/* CAN1 */
229&can2 {
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_flexcan2>;
232};
233
234/* SPI1 */
235&ecspi2 {
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_ecspi2>;
238 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>,
239 <&gpio2 27 GPIO_ACTIVE_LOW>;
240};
241
242/* SPI0 */
243&ecspi4 {
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_ecspi4>;
246 cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>,
247 <&gpio3 29 GPIO_ACTIVE_LOW>;
248 status = "okay";
249
250 /* default boot source: workaround #1 for errata ERR006282 */
251 smarc_flash: flash@0 {
252 compatible = "jedec,spi-nor";
253 reg = <0>;
254 spi-max-frequency = <20000000>;
255 };
256};
257
258/* GBE */
259&fec {
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_enet>;
262 phy-mode = "rgmii";
263 phy-handle = <&ethphy>;
264
265 mdio {
266 #address-cells = <1>;
267 #size-cells = <0>;
268
269 ethphy: ethernet-phy@1 {
270 compatible = "ethernet-phy-ieee802.3-c22";
271 reg = <1>;
272 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
273 reset-assert-us = <1000>;
274 };
275 };
276};
277
278&hdmi {
279 ddc-i2c-bus = <&i2c2>;
280};
281
282&i2c_intern {
283 pmic@8 {
284 compatible = "fsl,pfuze100";
285 reg = <0x08>;
286
287 regulators {
288 reg_v_core_s0: sw1ab {
289 regulator-name = "V_CORE_S0";
290 regulator-min-microvolt = <300000>;
291 regulator-max-microvolt = <1875000>;
292 regulator-boot-on;
293 regulator-always-on;
294 };
295
296 reg_vddsoc_s0: sw1c {
297 regulator-name = "V_VDDSOC_S0";
298 regulator-min-microvolt = <300000>;
299 regulator-max-microvolt = <1875000>;
300 regulator-boot-on;
301 regulator-always-on;
302 };
303
304 reg_3p15v_s0: sw2 {
305 regulator-name = "V_3V15_S0";
306 regulator-min-microvolt = <800000>;
307 regulator-max-microvolt = <3300000>;
308 regulator-boot-on;
309 regulator-always-on;
310 };
311
312 /* sw3a/b is used in dual mode, but driver does not
313 * support it. Although, there's no need to control
314 * DDR power - so just leaving dummy entries for sw3a
315 * and sw3b for now.
316 */
317 sw3a {
318 regulator-min-microvolt = <400000>;
319 regulator-max-microvolt = <1975000>;
320 regulator-boot-on;
321 regulator-always-on;
322 };
323
324 sw3b {
325 regulator-min-microvolt = <400000>;
326 regulator-max-microvolt = <1975000>;
327 regulator-boot-on;
328 regulator-always-on;
329 };
330
331 reg_1p8v_s0: sw4 {
332 regulator-name = "V_1V8_S0";
333 regulator-min-microvolt = <800000>;
334 regulator-max-microvolt = <3300000>;
335 regulator-boot-on;
336 regulator-always-on;
337 };
338
339 /* Regulator for USB */
340 reg_5p0v_s0: swbst {
341 regulator-name = "V_5V0_S0";
342 regulator-min-microvolt = <5000000>;
343 regulator-max-microvolt = <5150000>;
344 regulator-boot-on;
345 };
346
347 reg_vsnvs: vsnvs {
348 regulator-min-microvolt = <1000000>;
349 regulator-max-microvolt = <3000000>;
350 regulator-boot-on;
351 regulator-always-on;
352 };
353
354 reg_vrefddr: vrefddr {
355 regulator-boot-on;
356 regulator-always-on;
357 };
358
359 /*
360 * Per schematics, of all VGEN's, only VGEN5 has some
361 * usage ... but even that - over DNI resistor
362 */
363 vgen1 {
364 regulator-min-microvolt = <800000>;
365 regulator-max-microvolt = <1550000>;
366 };
367
368 vgen2 {
369 regulator-min-microvolt = <800000>;
370 regulator-max-microvolt = <1550000>;
371 };
372
373 vgen3 {
374 regulator-min-microvolt = <1800000>;
375 regulator-max-microvolt = <3300000>;
376 };
377
378 vgen4 {
379 regulator-min-microvolt = <1800000>;
380 regulator-max-microvolt = <3300000>;
381 };
382
383 reg_2p5v_s0: vgen5 {
384 regulator-name = "V_2V5_S0";
385 regulator-min-microvolt = <1800000>;
386 regulator-max-microvolt = <3300000>;
387 };
388
389 vgen6 {
390 regulator-min-microvolt = <1800000>;
391 regulator-max-microvolt = <3300000>;
392 };
393 };
394 };
395};
396
397/* I2C_GP */
398&i2c1 {
399 clock-frequency = <375000>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_i2c1>;
402};
403
404/* HDMI_CTRL */
405&i2c2 {
406 clock-frequency = <100000>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_i2c2>;
409};
410
411/* I2C_PM */
412&i2c3 {
413 clock-frequency = <375000>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_i2c3>;
416 status = "okay";
417
418 smarc_eeprom: eeprom@50 {
419 compatible = "atmel,24c32";
420 reg = <0x50>;
421 pagesize = <32>;
422 };
423};
424
425&iomuxc {
426 pinctrl-names = "default";
427 pinctrl-0 = <&pinctrl_mgmt_gpios &pinctrl_gpio>;
428
429 pinctrl_audmux: audmuxgrp {
430 fsl,pins = <
431 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
432 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0
433 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
434 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
435
436 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
437 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
438 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
439 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
440
441 /* AUDIO MCLK */
442 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0
443 >;
444 };
445
446 pinctrl_ecspi2: ecspi2grp {
447 fsl,pins = <
448 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
449 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
450 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
451
452 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 /* CS0 */
453 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* CS1 */
454 >;
455 };
456
457 pinctrl_ecspi4: ecspi4grp {
458 fsl,pins = <
459 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
460 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
461 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
462
463 /* SPI_IMX_CS2# - connected to internal flash */
464 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0
465 /* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */
466 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
467 >;
468 };
469
470 pinctrl_flexcan1: flexcan1grp {
471 fsl,pins = <
472 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
473 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
474 >;
475 };
476
477 pinctrl_flexcan2: flexcan2grp {
478 fsl,pins = <
479 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
480 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
481 >;
482 };
483
484 pinctrl_gpio: gpiogrp {
485 fsl,pins = <
486 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 /* GPIO0 / CAM0_PWR# */
487 MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 /* GPIO1 / CAM1_PWR# */
488 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 /* GPIO2 / CAM0_RST# */
489 MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 /* GPIO3 / CAM1_RST# */
490 MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 /* GPIO4 / HDA_RST# */
491 MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 /* GPIO5 / PWM_OUT */
492 MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 /* GPIO6 / TACHIN */
493 MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 /* GPIO7 / PCAM_FLD */
494 MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 /* GPIO8 / CAN0_ERR# */
495 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 /* GPIO9 / CAN1_ERR# */
496 MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /* GPIO10 */
497 MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b0 /* GPIO11 */
498 >;
499 };
500
501 pinctrl_enet: enetgrp {
502 fsl,pins = <
503 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
504 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
505 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
506 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
507 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
508 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
509 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
510 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
511 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
512 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
513 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
514 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
515
516 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
517 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
518 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
519 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */
520 >;
521 };
522
523 pinctrl_i2c_gpio_cam: i2c-gpiocamgrp {
524 fsl,pins = <
525 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* SCL */
526 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* SDA */
527 >;
528 };
529
530 pinctrl_i2c_gpio_intern: i2c-gpiointerngrp {
531 fsl,pins = <
532 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */
533 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */
534 >;
535 };
536
537 pinctrl_i2c_gpio_lcd: i2c-gpiolcdgrp {
538 fsl,pins = <
539 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 /* SCL */
540 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* SDA */
541 >;
542 };
543
544 pinctrl_i2c1: i2c1grp {
545 fsl,pins = <
546 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
547 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
548 >;
549 };
550
551 pinctrl_i2c2: i2c2grp {
552 fsl,pins = <
553 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
554 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
555 >;
556 };
557
558 pinctrl_i2c3: i2c3grp {
559 fsl,pins = <
560 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
561 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
562 >;
563 };
564
565 pinctrl_lcd: lcdgrp {
566 fsl,pins = <
567 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f1
568 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f1
569 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f1
570 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f1
571 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f1
572 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f1
573 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f1
574 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f1
575 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f1
576 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f1
577 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f1
578 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f1
579 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f1
580 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f1
581 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f1
582 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f1
583 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f1
584 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f1
585 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f1
586 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f1
587 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f1
588 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f1
589 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f1
590 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f1
591
592 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f1
593 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f1 /* DE */
594 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */
595 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f1 /* VSYNC */
596 >;
597 };
598
599 pinctrl_lcdbklt_en: lcdbkltengrp {
600 fsl,pins = <
601 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b1
602 >;
603 };
604
605 pinctrl_lcdvdd_en: lcdvddengrp {
606 fsl,pins = <
607 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
608 >;
609 };
610
611 pinctrl_mipi_csi: mipi-csigrp {
612 fsl,pins = <
613 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x000b0 /* CSI0/1 MCLK */
614 >;
615 };
616
617 pinctrl_mgmt_gpios: mgmt-gpiosgrp {
618 fsl,pins = <
619 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /* LID# */
620 MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x1b0b0 /* SLEEP# */
621 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* CHARGING# */
622 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* CHARGER_PRSNT# */
623 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 /* CARRIER_STBY# */
624 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* BATLOW# */
625 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 /* TEST# */
626 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* VDD_IO_SEL_D# */
627 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* POWER_BTN# */
628 >;
629 };
630
631 pinctrl_pcie: pciegrp {
632 fsl,pins = <
633 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */
634 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */
635 MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */
636 >;
637 };
638
639 pinctrl_pwm4: pwm4grp {
640 fsl,pins = <
641 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
642 >;
643 };
644
645 pinctrl_uart1: uart1grp {
646 fsl,pins = <
647 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
648 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
649 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
650 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
651 >;
652 };
653
654 pinctrl_uart2: uart2grp {
655 fsl,pins = <
656 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
657 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
658 >;
659 };
660
661 pinctrl_uart4: uart4grp {
662 fsl,pins = <
663 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
664 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
665 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
666 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
667 >;
668 };
669
670 pinctrl_uart5: uart5grp {
671 fsl,pins = <
672 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
673 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
674 >;
675 };
676
677 pinctrl_usbotg: usbotggrp {
678 fsl,pins = <
679 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0
680 /* power, oc muxed but not used by the driver */
681 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */
682 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */
683 >;
684 };
685
686 pinctrl_usdhc3: usdhc3grp {
687 fsl,pins = <
688 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x17059
689 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
690 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
691 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
692 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
693 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
694
695 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */
696 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */
697 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */
698 >;
699 };
700
701 pinctrl_usdhc4: usdhc4grp {
702 fsl,pins = <
703 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
704 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
705 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
706 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
707 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
708 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
709 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
710 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
711 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
712 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
713 >;
714 };
715
716 pinctrl_wdog1: wdog1rp {
717 fsl,pins = <
718 MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
719 >;
720 };
721};
722
723&mipi_csi {
724 pinctrl-names = "default";
725 pinctrl-0 = <&pinctrl_mipi_csi>;
726};
727
728&pcie {
729 pinctrl-names = "default";
730 pinctrl-0 = <&pinctrl_pcie>;
731 wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>;
732 reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
733};
734
735/* LCD_BKLT_PWM */
736&pwm4 {
737 pinctrl-names = "default";
738 pinctrl-0 = <&pinctrl_pwm4>;
739};
740
741&reg_arm {
742 vin-supply = <&reg_v_core_s0>;
743};
744
745&reg_pu {
746 vin-supply = <&reg_vddsoc_s0>;
747};
748
749&reg_soc {
750 vin-supply = <&reg_vddsoc_s0>;
751};
752
753/* SER0 */
754&uart1 {
755 pinctrl-names = "default";
756 pinctrl-0 = <&pinctrl_uart1>;
757 uart-has-rtscts;
758};
759
760/* SER1 */
761&uart2 {
762 pinctrl-names = "default";
763 pinctrl-0 = <&pinctrl_uart2>;
764};
765
766/* SER2 */
767&uart4 {
768 pinctrl-names = "default";
769 pinctrl-0 = <&pinctrl_uart4>;
770 uart-has-rtscts;
771};
772
773/* SER3 */
774&uart5 {
775 pinctrl-names = "default";
776 pinctrl-0 = <&pinctrl_uart5>;
777};
778
779/* USB0 */
780&usbotg {
781 /*
782 * no 'imx6-usb-charger-detection'
783 * since USB_OTG_CHD_B pin is not wired
784 */
785 pinctrl-names = "default";
786 pinctrl-0 = <&pinctrl_usbotg>;
787};
788
789/* USB1/2 via hub */
790&usbh1 {
791 vbus-supply = <&reg_5p0v_s0>;
792};
793
794/* SDIO */
795&usdhc3 {
796 pinctrl-names = "default";
797 pinctrl-0 = <&pinctrl_usdhc3>;
798 cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
799 wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
800 no-1-8-v;
801};
802
803/* SDMMC */
804&usdhc4 {
805 /* Internal eMMC, optional on some boards */
806 pinctrl-names = "default";
807 pinctrl-0 = <&pinctrl_usdhc4>;
808 bus-width = <8>;
809 no-sdio;
810 no-sd;
811 non-removable;
812 vmmc-supply = <&reg_3p3v_s0>;
813 vqmmc-supply = <&reg_1p8v_s0>;
814};
815
816&wdog1 {
817 /* CPLD is feeded by watchdog (hardwired) */
818 pinctrl-names = "default";
819 pinctrl-0 = <&pinctrl_wdog1>;
820 status = "okay";
821};