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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / nxp / imx / imx53-smd.dts
blob: 55435dfdff8aadff841c15ec99cdda524b7cfaf2 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2011 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6/dts-v1/;
7#include <dt-bindings/input/input.h>
8#include "imx53.dtsi"
9
10/ {
11 model = "Freescale i.MX53 Smart Mobile Reference Design Board";
12 compatible = "fsl,imx53-smd", "fsl,imx53";
13
14 memory@70000000 {
15 device_type = "memory";
16 reg = <0x70000000 0x40000000>;
17 };
18
19 gpio-keys {
20 compatible = "gpio-keys";
21
22 key-volume-up {
23 label = "Volume Up";
24 gpios = <&gpio2 14 0>;
25 linux,code = <KEY_VOLUMEUP>;
26 };
27
28 key-volume-down {
29 label = "Volume Down";
30 gpios = <&gpio2 15 0>;
31 linux,code = <KEY_VOLUMEDOWN>;
32 };
33 };
34};
35
36&esdhc1 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_esdhc1>;
39 cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
40 wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
41 status = "okay";
42};
43
44&esdhc2 {
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_esdhc2>;
47 non-removable;
48 status = "okay";
49};
50
51&uart3 {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_uart3>;
54 uart-has-rtscts;
55 status = "okay";
56};
57
58&ecspi1 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_ecspi1>;
61 cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>;
62 status = "okay";
63
64 zigbee: mc1323@0 {
65 compatible = "fsl,mc1323";
66 spi-max-frequency = <8000000>;
67 reg = <0>;
68 };
69
70 flash: flash@1 {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 compatible = "st,m25p32", "jedec,spi-nor";
74 spi-max-frequency = <20000000>;
75 reg = <1>;
76
77 partition@0 {
78 label = "U-Boot";
79 reg = <0x0 0x40000>;
80 read-only;
81 };
82
83 partition@40000 {
84 label = "Kernel";
85 reg = <0x40000 0x3c0000>;
86 };
87 };
88};
89
90&esdhc3 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_esdhc3>;
93 non-removable;
94 status = "okay";
95};
96
97&iomuxc {
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_hog>;
100
101 imx53-smd {
102 pinctrl_hog: hoggrp {
103 fsl,pins = <
104 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
105 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
106 MX53_PAD_EIM_EB2__GPIO2_30 0x80000000
107 MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
108 MX53_PAD_EIM_D19__GPIO3_19 0x80000000
109 MX53_PAD_KEY_ROW2__GPIO4_11 0x80000000
110 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
111 >;
112 };
113
114 pinctrl_ecspi1: ecspi1grp {
115 fsl,pins = <
116 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
117 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
118 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
119 >;
120 };
121
122 pinctrl_esdhc1: esdhc1grp {
123 fsl,pins = <
124 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
125 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
126 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
127 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
128 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
129 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
130 >;
131 };
132
133 pinctrl_esdhc2: esdhc2grp {
134 fsl,pins = <
135 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
136 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
137 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
138 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
139 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
140 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
141 >;
142 };
143
144 pinctrl_esdhc3: esdhc3grp {
145 fsl,pins = <
146 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
147 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
148 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
149 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
150 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
151 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
152 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
153 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
154 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
155 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
156 >;
157 };
158
159 pinctrl_fec: fecgrp {
160 fsl,pins = <
161 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
162 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
163 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
164 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
165 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
166 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
167 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
168 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
169 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
170 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
171 >;
172 };
173
174 pinctrl_i2c1: i2c1grp {
175 fsl,pins = <
176 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
177 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
178 >;
179 };
180
181 pinctrl_i2c2: i2c2grp {
182 fsl,pins = <
183 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
184 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
185 >;
186 };
187
188 pinctrl_ipu_csi0: ipucsi0grp {
189 fsl,pins = <
190 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1c4
191 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1c4
192 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1c4
193 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1c4
194 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1c4
195 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1c4
196 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1c4
197 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1c4
198 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1e4
199 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1e4
200 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1e4
201 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1e4
202 >;
203 };
204
205 pinctrl_ov5642: ov5642grp {
206 fsl,pins = <
207 MX53_PAD_NANDF_WP_B__GPIO6_9 0x1e4
208 MX53_PAD_NANDF_RB0__GPIO6_10 0x1e4
209 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
210 >;
211 };
212
213 pinctrl_uart1: uart1grp {
214 fsl,pins = <
215 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
216 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
217 >;
218 };
219
220 pinctrl_uart2: uart2grp {
221 fsl,pins = <
222 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
223 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
224 >;
225 };
226
227 pinctrl_uart3: uart3grp {
228 fsl,pins = <
229 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
230 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
231 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
232 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
233 >;
234 };
235 };
236};
237
238&uart1 {
239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_uart1>;
241 status = "okay";
242};
243
244&uart2 {
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_uart2>;
247 status = "okay";
248};
249
250&i2c2 {
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_i2c2>;
253 status = "okay";
254
255 codec: sgtl5000@a {
256 compatible = "fsl,sgtl5000";
257 reg = <0x0a>;
258 };
259
260 magnetometer: mag3110@e {
261 compatible = "fsl,mag3110";
262 reg = <0x0e>;
263 };
264
265 touchkey: mpr121@5a {
266 compatible = "fsl,mpr121";
267 reg = <0x5a>;
268 };
269};
270
271&i2c1 {
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_i2c1>;
274 status = "okay";
275
276 accelerometer: mma8450@1c {
277 compatible = "fsl,mma8450";
278 reg = <0x1c>;
279 };
280
281 camera: ov5642@3c {
282 compatible = "ovti,ov5642";
283 reg = <0x3c>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_ov5642>;
286 assigned-clocks = <&clks IMX5_CLK_SSI_EXT1_SEL>,
287 <&clks IMX5_CLK_SSI_EXT1_COM_SEL>;
288 assigned-clock-parents = <&clks IMX5_CLK_PLL2_SW>,
289 <&clks IMX5_CLK_SSI_EXT1_PODF>;
290 assigned-clock-rates = <0>, <24000000>;
291 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
292 clock-names = "xclk";
293 DVDD-supply = <&ldo9_reg>;
294 AVDD-supply = <&ldo7_reg>;
295 reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>;
296 powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;
297
298 port {
299 ov5642_to_ipu_csi0: endpoint {
300 remote-endpoint = <&ipu_csi0_from_parallel_sensor>;
301 bus-width = <8>;
302 hsync-active = <1>;
303 vsync-active = <1>;
304 };
305 };
306 };
307
308 pmic: dialog@48 {
309 compatible = "dlg,da9053", "dlg,da9052";
310 reg = <0x48>;
311 interrupt-parent = <&gpio7>;
312 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
313
314 regulators {
315 ldo7_reg: ldo7 {
316 regulator-min-microvolt = <1200000>;
317 regulator-max-microvolt = <3600000>;
318 };
319
320 ldo9_reg: ldo9 {
321 regulator-min-microvolt = <1250000>;
322 regulator-max-microvolt = <3650000>;
323 };
324 };
325 };
326};
327
328&fec {
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_fec>;
331 phy-mode = "rmii";
332 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
333 status = "okay";
334};
335
336&ipu_csi0_from_parallel_sensor {
337 remote-endpoint = <&ov5642_to_ipu_csi0>;
338 data-shift = <12>; /* Lines 19:12 used */
339 hsync-active = <1>;
340 vsync-active = <1>;
341};
342
343&ipu_csi0 {
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_ipu_csi0>;
346};