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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / nxp / imx / imx51-zii-scu2-mezz.dts
blob: 625f9ac671ae9713110fcd2cf62884c8fd79f236 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
3/*
4 * Copyright (C) 2018 Zodiac Inflight Innovations
5 */
6
7/dts-v1/;
8
9#include "imx51.dtsi"
10
11/ {
12 model = "ZII SCU2 Mezz Board";
13 compatible = "zii,imx51-scu2-mezz", "fsl,imx51";
14
15 chosen {
16 stdout-path = &uart1;
17 };
18
19 /* Will be filled by the bootloader */
20 memory@90000000 {
21 device_type = "memory";
22 reg = <0x90000000 0>;
23 };
24
25 aliases {
26 mdio-gpio0 = &mdio_gpio;
27 };
28
29 usb_vbus: regulator-usb-vbus {
30 compatible = "regulator-fixed";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_usb_mmc_reset>;
33 gpio = <&gpio3 13 GPIO_ACTIVE_LOW>;
34 startup-delay-us = <150000>;
35 regulator-name = "usb_vbus";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
38 };
39
40 mdio_gpio: mdio-gpio {
41 compatible = "virtual,mdio-gpio";
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_swmdio>;
44 gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>, /* mdc */
45 <&gpio2 6 GPIO_ACTIVE_HIGH>; /* mdio */
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 switch@0 {
50 compatible = "marvell,mv88e6085";
51 reg = <0>;
52 dsa,member = <0 0>;
53 eeprom-length = <512>;
54 interrupt-parent = <&gpio1>;
55 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
56 interrupt-controller;
57 #interrupt-cells = <2>;
58
59 ports {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 port@0 {
64 reg = <0>;
65 label = "port4";
66 };
67
68 port@1 {
69 reg = <1>;
70 label = "port5";
71 };
72
73 port@2 {
74 reg = <2>;
75 label = "port6";
76 };
77
78 port@3 {
79 reg = <3>;
80 label = "port7";
81 };
82
83 port@4 {
84 reg = <4>;
85 phy-mode = "rev-mii";
86 ethernet = <&fec>;
87
88 fixed-link {
89 speed = <100>;
90 full-duplex;
91 };
92 };
93
94 port@5 {
95 reg = <5>;
96 label = "mezz2esb";
97 phy-mode = "sgmii";
98
99 fixed-link {
100 speed = <1000>;
101 full-duplex;
102 };
103 };
104 };
105 };
106 };
107};
108
109&cpu {
110 cpu-supply = <&sw1_reg>;
111};
112
113&ecspi1 {
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_ecspi1>;
116 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
117 <&gpio4 25 GPIO_ACTIVE_LOW>;
118 status = "okay";
119
120 pmic@0 {
121 compatible = "fsl,mc13892";
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_pmic>;
124 spi-max-frequency = <6000000>;
125 spi-cs-high;
126 reg = <0>;
127 interrupt-parent = <&gpio1>;
128 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
129 fsl,mc13xxx-uses-adc;
130
131 regulators {
132 sw1_reg: sw1 {
133 regulator-min-microvolt = <600000>;
134 regulator-max-microvolt = <1375000>;
135 regulator-boot-on;
136 regulator-always-on;
137 };
138
139 sw2_reg: sw2 {
140 regulator-min-microvolt = <900000>;
141 regulator-max-microvolt = <1850000>;
142 regulator-boot-on;
143 regulator-always-on;
144 };
145
146 sw3_reg: sw3 {
147 regulator-min-microvolt = <1100000>;
148 regulator-max-microvolt = <1850000>;
149 regulator-boot-on;
150 regulator-always-on;
151 };
152
153 sw4_reg: sw4 {
154 regulator-min-microvolt = <1100000>;
155 regulator-max-microvolt = <1850000>;
156 regulator-boot-on;
157 regulator-always-on;
158 };
159
160 vpll_reg: vpll {
161 regulator-min-microvolt = <1050000>;
162 regulator-max-microvolt = <1800000>;
163 regulator-boot-on;
164 regulator-always-on;
165 };
166
167 vdig_reg: vdig {
168 regulator-min-microvolt = <1650000>;
169 regulator-max-microvolt = <1650000>;
170 regulator-boot-on;
171 };
172
173 vsd_reg: vsd {
174 regulator-min-microvolt = <1800000>;
175 regulator-max-microvolt = <3150000>;
176 regulator-always-on;
177 };
178
179 vusb_reg: vusb {
180 regulator-always-on;
181 };
182
183 vusb2_reg: vusb2 {
184 regulator-min-microvolt = <2400000>;
185 regulator-max-microvolt = <2775000>;
186 regulator-boot-on;
187 regulator-always-on;
188 };
189
190 vvideo_reg: vvideo {
191 regulator-min-microvolt = <2775000>;
192 regulator-max-microvolt = <2775000>;
193 };
194
195 vaudio_reg: vaudio {
196 regulator-min-microvolt = <2300000>;
197 regulator-max-microvolt = <3000000>;
198 };
199
200 vcam_reg: vcam {
201 regulator-min-microvolt = <2500000>;
202 regulator-max-microvolt = <3000000>;
203 };
204
205 vgen1_reg: vgen1 {
206 regulator-min-microvolt = <1200000>;
207 regulator-max-microvolt = <1200000>;
208 };
209
210 vgen2_reg: vgen2 {
211 regulator-min-microvolt = <1200000>;
212 regulator-max-microvolt = <3150000>;
213 regulator-always-on;
214 };
215
216 vgen3_reg: vgen3 {
217 regulator-min-microvolt = <1800000>;
218 regulator-max-microvolt = <2900000>;
219 regulator-always-on;
220 };
221 };
222
223 leds {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 led-control = <0x0 0x0 0x3f83f8 0x0>;
227
228 sysled3: led3@3 {
229 reg = <3>;
230 label = "system:red:power";
231 linux,default-trigger = "default-on";
232 };
233
234 sysled4: led4@4 {
235 reg = <4>;
236 label = "system:green:act";
237 linux,default-trigger = "heartbeat";
238 };
239 };
240 };
241
242 flash@1 {
243 compatible = "atmel,at45", "atmel,dataflash";
244 reg = <1>;
245 spi-max-frequency = <25000000>;
246 };
247};
248
249&esdhc1 {
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_esdhc1>;
252 bus-width = <8>;
253 non-removable;
254 no-1-8-v;
255 no-sdio;
256 no-sd;
257 status = "okay";
258};
259
260&esdhc4 {
261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_esdhc4>;
263 bus-width = <4>;
264 no-1-8-v;
265 no-sdio;
266 cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
267 status = "okay";
268};
269
270&fec {
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_fec>;
273 phy-mode = "mii";
274 status = "okay";
275 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
276 phy-reset-duration = <1>;
277 phy-supply = <&vgen3_reg>;
278 phy-handle = <&ethphy>;
279
280 mdio {
281 #address-cells = <1>;
282 #size-cells = <0>;
283
284 ethphy: ethernet-phy@0 {
285 reg = <0>;
286 max-speed = <100>;
287 };
288 };
289};
290
291&i2c2 {
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_i2c2>;
294 status = "okay";
295
296 eeprom@50 {
297 compatible = "atmel,24c04";
298 pagesize = <16>;
299 reg = <0x50>;
300 };
301};
302
303&uart1 {
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_uart1>;
306 status = "okay";
307};
308
309&uart3 {
310 pinctrl-names = "default";
311 pinctrl-0 = <&pinctrl_uart3>;
312 status = "okay";
313
314 mcu {
315 compatible = "zii,rave-sp-mezz";
316 current-speed = <57600>;
317 #address-cells = <1>;
318 #size-cells = <1>;
319
320 watchdog {
321 compatible = "zii,rave-sp-watchdog-legacy";
322 };
323
324 eeprom@a4 {
325 compatible = "zii,rave-sp-eeprom";
326 reg = <0xa4 0x4000>;
327 #address-cells = <1>;
328 #size-cells = <1>;
329 zii,eeprom-name = "main-eeprom";
330 };
331 };
332};
333
334&usbotg {
335 dr_mode = "host";
336 disable-over-current;
337 phy_type = "utmi_wide";
338 vbus-supply = <&usb_vbus>;
339 status = "okay";
340};
341
342&usbphy0 {
343 vcc-supply = <&vusb2_reg>;
344};
345
346&vpu {
347 status = "disabled";
348};
349
350&wdog1 {
351 status = "disabled";
352};
353
354&iomuxc {
355 pinctrl_ecspi1: ecspi1grp {
356 fsl,pins = <
357 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
358 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
359 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
360 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
361 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
362 >;
363 };
364
365 pinctrl_esdhc1: esdhc1grp {
366 fsl,pins = <
367 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
368 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
369 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
370 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
371 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
372 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
373 MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5
374 MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5
375 MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5
376 MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5
377 >;
378 };
379
380 pinctrl_esdhc4: esdhc4grp {
381 fsl,pins = <
382 MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5
383 MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5
384 MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5
385 MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5
386 MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5
387 MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5
388 MX51_PAD_NANDF_D0__GPIO4_8 0x100
389 >;
390 };
391
392 pinctrl_fec: fecgrp {
393 fsl,pins = <
394 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004
395 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004
396 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004
397 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004
398 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004
399 MX51_PAD_DISP2_DAT10__FEC_COL 0x0180
400 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180
401 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4
402 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x20a4
403 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180
404 MX51_PAD_DI_GP3__FEC_TX_ER 0x2004
405 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180
406 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085
407 MX51_PAD_DI_GP4__FEC_RDATA2 0x0085
408 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085
409 MX51_PAD_DI2_PIN2__FEC_MDC 0x2004
410 MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5
411 MX51_PAD_DI2_PIN4__FEC_CRS 0x0180
412 MX51_PAD_EIM_A20__GPIO2_14 0x0085
413 MX51_PAD_EIM_A21__GPIO2_15 0x00e5
414 >;
415 };
416
417 pinctrl_i2c2: i2c2grp {
418 fsl,pins = <
419 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
420 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
421 >;
422 };
423
424 pinctrl_pmic: pmicgrp {
425 fsl,pins = <
426 MX51_PAD_GPIO1_4__GPIO1_4 0x85
427 MX51_PAD_GPIO1_8__GPIO1_8 0xe5
428 >;
429 };
430
431 pinctrl_swmdio: swmdiogrp {
432 fsl,pins = <
433 MX51_PAD_EIM_D22__GPIO2_6 0x100
434 MX51_PAD_EIM_D23__GPIO2_7 0x100
435 >;
436 };
437
438 pinctrl_uart1: uart1grp {
439 fsl,pins = <
440 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
441 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
442 >;
443 };
444
445 pinctrl_uart3: uart3grp {
446 fsl,pins = <
447 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
448 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
449 >;
450 };
451
452 pinctrl_usb_mmc_reset: usbmmcgrp {
453 fsl,pins = <
454 MX51_PAD_CSI1_D9__GPIO3_13 0x85
455 >;
456 };
457};