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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / nxp / imx / imx51-babbage.dts
blob: 16ff543f3fbf88c58f25017eda2fdf31644abdf0 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2011 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6/dts-v1/;
7#include "imx51.dtsi"
8
9/ {
10 model = "Freescale i.MX51 Babbage Board";
11 compatible = "fsl,imx51-babbage", "fsl,imx51";
12
13 chosen {
14 stdout-path = &uart1;
15 };
16
17 memory@90000000 {
18 device_type = "memory";
19 reg = <0x90000000 0x20000000>;
20 };
21
22 ckih1 {
23 clock-frequency = <22579200>;
24 };
25
26 clk_osc: clk-osc {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <26000000>;
30 };
31
32 clk_osc_gate: clk-osc-gate {
33 compatible = "gpio-gate-clock";
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_clk26mhz_osc>;
36 clocks = <&clk_osc>;
37 #clock-cells = <0>;
38 enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
39 };
40
41 clk_audio: clk-audio {
42 compatible = "gpio-gate-clock";
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_clk26mhz_audio>;
45 clocks = <&clk_osc_gate>;
46 #clock-cells = <0>;
47 enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
48 };
49
50 clk_usb: clk-usb {
51 compatible = "gpio-gate-clock";
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_clk26mhz_usb>;
54 clocks = <&clk_osc_gate>;
55 #clock-cells = <0>;
56 enable-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
57 };
58
59 display1: disp1 {
60 compatible = "fsl,imx-parallel-display";
61 #address-cells = <1>;
62 #size-cells = <0>;
63 interface-pix-fmt = "rgb24";
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_ipu_disp1>;
66
67 port@0 {
68 reg = <0>;
69
70 display0_in: endpoint {
71 remote-endpoint = <&ipu_di0_disp1>;
72 };
73 };
74
75 port@1 {
76 reg = <1>;
77
78 parallel_display_out: endpoint {
79 remote-endpoint = <&tfp410_in>;
80 };
81 };
82 };
83
84 display2: disp2 {
85 compatible = "fsl,imx-parallel-display";
86 interface-pix-fmt = "rgb565";
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_ipu_disp2>;
89 status = "disabled";
90 display-timings {
91 native-mode = <&timing1>;
92 timing1: claawvga {
93 clock-frequency = <27000000>;
94 hactive = <800>;
95 vactive = <480>;
96 hback-porch = <40>;
97 hfront-porch = <60>;
98 vback-porch = <10>;
99 vfront-porch = <10>;
100 hsync-len = <20>;
101 vsync-len = <10>;
102 hsync-active = <0>;
103 vsync-active = <0>;
104 de-active = <1>;
105 pixelclk-active = <0>;
106 };
107 };
108
109 port {
110 display1_in: endpoint {
111 remote-endpoint = <&ipu_di1_disp2>;
112 };
113 };
114 };
115
116 dvi-connector {
117 compatible = "dvi-connector";
118 digital;
119
120 port {
121 dvi_connector_in: endpoint {
122 remote-endpoint = <&tfp410_out>;
123 };
124 };
125 };
126
127 dvi-encoder {
128 compatible = "ti,tfp410";
129
130 ports {
131 #address-cells = <1>;
132 #size-cells = <0>;
133
134 port@0 {
135 reg = <0>;
136
137 tfp410_in: endpoint {
138 remote-endpoint = <&parallel_display_out>;
139 };
140 };
141
142 port@1 {
143 reg = <1>;
144
145 tfp410_out: endpoint {
146 remote-endpoint = <&dvi_connector_in>;
147 };
148 };
149 };
150 };
151
152 gpio-keys {
153 compatible = "gpio-keys";
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_gpio_keys>;
156
157 key-power {
158 label = "Power Button";
159 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
160 linux,code = <KEY_POWER>;
161 wakeup-source;
162 };
163 };
164
165 leds {
166 compatible = "gpio-leds";
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_gpio_leds>;
169
170 led-diagnostic {
171 label = "diagnostic";
172 gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
173 };
174 };
175
176 reg_hub_reset: regulator-hub-reset {
177 compatible = "regulator-fixed";
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_usbotgreg>;
180 regulator-name = "hub_reset";
181 regulator-min-microvolt = <5000000>;
182 regulator-max-microvolt = <5000000>;
183 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
184 enable-active-high;
185 };
186
187 sound {
188 compatible = "fsl,imx51-babbage-sgtl5000",
189 "fsl,imx-audio-sgtl5000";
190 model = "imx51-babbage-sgtl5000";
191 ssi-controller = <&ssi2>;
192 audio-codec = <&sgtl5000>;
193 audio-routing =
194 "MIC_IN", "Mic Jack",
195 "Mic Jack", "Mic Bias",
196 "Headphone Jack", "HP_OUT";
197 mux-int-port = <2>;
198 mux-ext-port = <3>;
199 };
200
201 usbphy1: usbphy1 {
202 compatible = "usb-nop-xceiv";
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_usbh1reg>;
205 clocks = <&clk_usb>;
206 clock-names = "main_clk";
207 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
208 vcc-supply = <&vusb_reg>;
209 #phy-cells = <0>;
210 };
211};
212
213&audmux {
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_audmux>;
216 status = "okay";
217};
218
219&ecspi1 {
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_ecspi1>;
222 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
223 <&gpio4 25 GPIO_ACTIVE_LOW>;
224 status = "okay";
225
226 pmic: mc13892@0 {
227 compatible = "fsl,mc13892";
228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_pmic>;
230 spi-max-frequency = <6000000>;
231 spi-cs-high;
232 reg = <0>;
233 interrupt-parent = <&gpio1>;
234 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
235 fsl,mc13xxx-uses-adc;
236 fsl,mc13xxx-uses-rtc;
237
238 regulators {
239 sw1_reg: sw1 {
240 regulator-min-microvolt = <600000>;
241 regulator-max-microvolt = <1375000>;
242 regulator-boot-on;
243 regulator-always-on;
244 };
245
246 sw2_reg: sw2 {
247 regulator-min-microvolt = <900000>;
248 regulator-max-microvolt = <1850000>;
249 regulator-boot-on;
250 regulator-always-on;
251 };
252
253 sw3_reg: sw3 {
254 regulator-min-microvolt = <1100000>;
255 regulator-max-microvolt = <1850000>;
256 regulator-boot-on;
257 regulator-always-on;
258 };
259
260 sw4_reg: sw4 {
261 regulator-min-microvolt = <1100000>;
262 regulator-max-microvolt = <1850000>;
263 regulator-boot-on;
264 regulator-always-on;
265 };
266
267 vpll_reg: vpll {
268 regulator-min-microvolt = <1050000>;
269 regulator-max-microvolt = <1800000>;
270 regulator-boot-on;
271 regulator-always-on;
272 };
273
274 vdig_reg: vdig {
275 regulator-min-microvolt = <1650000>;
276 regulator-max-microvolt = <1650000>;
277 regulator-boot-on;
278 };
279
280 vsd_reg: vsd {
281 regulator-min-microvolt = <1800000>;
282 regulator-max-microvolt = <3150000>;
283 };
284
285 vusb_reg: vusb {
286 regulator-boot-on;
287 };
288
289 vusb2_reg: vusb2 {
290 regulator-min-microvolt = <2400000>;
291 regulator-max-microvolt = <2775000>;
292 regulator-boot-on;
293 regulator-always-on;
294 };
295
296 vvideo_reg: vvideo {
297 regulator-min-microvolt = <2775000>;
298 regulator-max-microvolt = <2775000>;
299 };
300
301 vaudio_reg: vaudio {
302 regulator-min-microvolt = <2300000>;
303 regulator-max-microvolt = <3000000>;
304 };
305
306 vcam_reg: vcam {
307 regulator-min-microvolt = <2500000>;
308 regulator-max-microvolt = <3000000>;
309 };
310
311 vgen1_reg: vgen1 {
312 regulator-min-microvolt = <1200000>;
313 regulator-max-microvolt = <1200000>;
314 };
315
316 vgen2_reg: vgen2 {
317 regulator-min-microvolt = <1200000>;
318 regulator-max-microvolt = <3150000>;
319 regulator-always-on;
320 };
321
322 vgen3_reg: vgen3 {
323 regulator-min-microvolt = <1800000>;
324 regulator-max-microvolt = <2900000>;
325 regulator-always-on;
326 };
327 };
328 };
329
330 flash: at45db321d@1 {
331 #address-cells = <1>;
332 #size-cells = <1>;
333 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
334 spi-max-frequency = <25000000>;
335 reg = <1>;
336
337 partition@0 {
338 label = "U-Boot";
339 reg = <0x0 0x40000>;
340 read-only;
341 };
342
343 partition@40000 {
344 label = "Kernel";
345 reg = <0x40000 0x3c0000>;
346 };
347 };
348};
349
350&esdhc1 {
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_esdhc1>;
353 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
354 wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
355 status = "okay";
356};
357
358&esdhc2 {
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_esdhc2>;
361 cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
362 wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
363 status = "okay";
364};
365
366&fec {
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_fec>;
369 phy-mode = "mii";
370 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
371 phy-reset-duration = <1>;
372 status = "okay";
373};
374
375&i2c1 {
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_i2c1>;
378 status = "okay";
379};
380
381&i2c2 {
382 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_i2c2>;
384 status = "okay";
385
386 sgtl5000: codec@a {
387 compatible = "fsl,sgtl5000";
388 reg = <0x0a>;
389 #sound-dai-cells = <0>;
390 clocks = <&clk_audio>;
391 VDDA-supply = <&vdig_reg>;
392 VDDIO-supply = <&vvideo_reg>;
393 };
394};
395
396&ipu_di0_disp1 {
397 remote-endpoint = <&display0_in>;
398};
399
400&ipu_di1_disp2 {
401 remote-endpoint = <&display1_in>;
402};
403
404&kpp {
405 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_kpp>;
407 linux,keymap = <
408 MATRIX_KEY(0, 0, KEY_UP)
409 MATRIX_KEY(0, 1, KEY_DOWN)
410 MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
411 MATRIX_KEY(0, 3, KEY_HOME)
412 MATRIX_KEY(1, 0, KEY_RIGHT)
413 MATRIX_KEY(1, 1, KEY_LEFT)
414 MATRIX_KEY(1, 2, KEY_ENTER)
415 MATRIX_KEY(1, 3, KEY_VOLUMEUP)
416 MATRIX_KEY(2, 0, KEY_F6)
417 MATRIX_KEY(2, 1, KEY_F8)
418 MATRIX_KEY(2, 2, KEY_F9)
419 MATRIX_KEY(2, 3, KEY_F10)
420 MATRIX_KEY(3, 0, KEY_F1)
421 MATRIX_KEY(3, 1, KEY_F2)
422 MATRIX_KEY(3, 2, KEY_F3)
423 MATRIX_KEY(3, 3, KEY_POWER)
424 >;
425 status = "okay";
426};
427
428&pmu {
429 secure-reg-access;
430};
431
432&ssi2 {
433 status = "okay";
434};
435
436&uart1 {
437 pinctrl-names = "default";
438 pinctrl-0 = <&pinctrl_uart1>;
439 uart-has-rtscts;
440 status = "okay";
441};
442
443&uart2 {
444 pinctrl-names = "default";
445 pinctrl-0 = <&pinctrl_uart2>;
446 status = "okay";
447};
448
449&uart3 {
450 pinctrl-names = "default";
451 pinctrl-0 = <&pinctrl_uart3>;
452 uart-has-rtscts;
453 status = "okay";
454};
455
456&usbh1 {
457 pinctrl-names = "default";
458 pinctrl-0 = <&pinctrl_usbh1>;
459 vbus-supply = <&reg_hub_reset>;
460 fsl,usbphy = <&usbphy1>;
461 phy_type = "ulpi";
462 status = "okay";
463};
464
465&usbphy0 {
466 vcc-supply = <&vusb_reg>;
467};
468
469&usbotg {
470 dr_mode = "otg";
471 disable-over-current;
472 phy_type = "utmi_wide";
473 status = "okay";
474};
475
476&iomuxc {
477 imx51-babbage {
478 pinctrl_audmux: audmuxgrp {
479 fsl,pins = <
480 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
481 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
482 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
483 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
484 >;
485 };
486
487 pinctrl_clk26mhz_audio: clk26mhzaudiocgrp {
488 fsl,pins = <
489 MX51_PAD_CSPI1_RDY__GPIO4_26 0x85
490 >;
491 };
492
493 pinctrl_clk26mhz_osc: clk26mhzoscgrp {
494 fsl,pins = <
495 MX51_PAD_DI1_PIN12__GPIO3_1 0x85
496 >;
497 };
498
499 pinctrl_clk26mhz_usb: clk26mhzusbgrp {
500 fsl,pins = <
501 MX51_PAD_EIM_D17__GPIO2_1 0x85
502 >;
503 };
504
505 pinctrl_ecspi1: ecspi1grp {
506 fsl,pins = <
507 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
508 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
509 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
510 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
511 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */
512 >;
513 };
514
515 pinctrl_esdhc1: esdhc1grp {
516 fsl,pins = <
517 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
518 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
519 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
520 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
521 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
522 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
523 MX51_PAD_GPIO1_0__GPIO1_0 0x100
524 MX51_PAD_GPIO1_1__GPIO1_1 0x100
525 >;
526 };
527
528 pinctrl_esdhc2: esdhc2grp {
529 fsl,pins = <
530 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
531 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
532 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
533 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
534 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
535 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
536 MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */
537 MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */
538 >;
539 };
540
541 pinctrl_fec: fecgrp {
542 fsl,pins = <
543 MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
544 MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
545 MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
546 MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
547 MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
548 MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
549 MX51_PAD_NANDF_RB2__FEC_COL 0x00000180
550 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180
551 MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180
552 MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004
553 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
554 MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004
555 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004
556 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004
557 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004
558 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004
559 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180
560 MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4
561 MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
562 >;
563 };
564
565 pinctrl_gpio_keys: gpiokeysgrp {
566 fsl,pins = <
567 MX51_PAD_EIM_A27__GPIO2_21 0x5
568 >;
569 };
570
571 pinctrl_gpio_leds: gpioledsgrp {
572 fsl,pins = <
573 MX51_PAD_EIM_D22__GPIO2_6 0x80000000
574 >;
575 };
576
577 pinctrl_i2c1: i2c1grp {
578 fsl,pins = <
579 MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed
580 MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed
581 >;
582 };
583
584 pinctrl_i2c2: i2c2grp {
585 fsl,pins = <
586 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
587 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
588 >;
589 };
590
591 pinctrl_ipu_disp1: ipudisp1grp {
592 fsl,pins = <
593 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
594 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
595 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
596 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
597 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
598 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
599 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
600 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
601 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
602 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
603 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
604 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
605 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
606 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
607 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
608 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
609 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
610 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
611 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
612 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
613 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
614 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
615 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
616 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
617 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
618 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
619 >;
620 };
621
622 pinctrl_ipu_disp2: ipudisp2grp {
623 fsl,pins = <
624 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
625 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
626 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
627 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
628 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
629 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
630 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
631 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
632 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
633 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
634 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
635 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
636 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
637 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
638 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
639 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
640 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
641 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
642 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
643 MX51_PAD_DI_GP4__DI2_PIN15 0x5
644 >;
645 };
646
647 pinctrl_kpp: kppgrp {
648 fsl,pins = <
649 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
650 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
651 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
652 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
653 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
654 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
655 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
656 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
657 >;
658 };
659
660 pinctrl_pmic: pmicgrp {
661 fsl,pins = <
662 MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */
663 >;
664 };
665
666 pinctrl_uart1: uart1grp {
667 fsl,pins = <
668 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
669 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
670 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
671 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
672 >;
673 };
674
675 pinctrl_uart2: uart2grp {
676 fsl,pins = <
677 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
678 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
679 >;
680 };
681
682 pinctrl_uart3: uart3grp {
683 fsl,pins = <
684 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
685 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
686 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
687 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
688 >;
689 };
690
691 pinctrl_usbh1: usbh1grp {
692 fsl,pins = <
693 MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000
694 MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000
695 MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000
696 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000
697 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000
698 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000
699 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000
700 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000
701 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000
702 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000
703 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000
704 >;
705 };
706
707 pinctrl_usbh1reg: usbh1reggrp {
708 fsl,pins = <
709 MX51_PAD_EIM_D21__GPIO2_5 0x85
710 >;
711 };
712
713 pinctrl_usbotgreg: usbotgreggrp {
714 fsl,pins = <
715 MX51_PAD_GPIO1_7__GPIO1_7 0x85
716 >;
717 };
718 };
719};