Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> |
| 4 | */ |
| 5 | |
| 6 | / { |
| 7 | #address-cells = <1>; |
| 8 | #size-cells = <1>; |
| 9 | interrupt-parent = <&intc>; |
| 10 | |
| 11 | cpus { |
| 12 | #address-cells = <1>; |
| 13 | #size-cells = <0>; |
| 14 | |
| 15 | cpu@0 { |
| 16 | compatible = "arm,arm926ej-s"; |
| 17 | device_type = "cpu"; |
| 18 | reg = <0>; |
| 19 | }; |
| 20 | }; |
| 21 | |
| 22 | bootrom: bootrom@0 { |
| 23 | reg = <0x00000000 0x80000>; |
| 24 | }; |
| 25 | |
| 26 | sram: sram@a4000000 { |
| 27 | compatible = "mmio-sram"; |
| 28 | reg = <0xa4000000 0x20000>; /* 128k */ |
| 29 | #address-cells = <1>; |
| 30 | #size-cells = <1>; |
| 31 | ranges = <0 0xa4000000 0x20000>; |
| 32 | |
| 33 | sram@0 { |
| 34 | reg = <0x0 0x20000>; |
| 35 | }; |
| 36 | }; |
| 37 | |
| 38 | timer_clk: timer_clk { |
| 39 | #clock-cells = <0>; |
| 40 | compatible = "fixed-clock"; |
| 41 | clock-frequency = <32768>; |
| 42 | }; |
| 43 | |
| 44 | base_clk: base_clk { |
| 45 | #clock-cells = <0>; |
| 46 | reg = <0x900b0024 0x4>; |
| 47 | }; |
| 48 | |
| 49 | ahb_clk: ahb_clk { |
| 50 | #clock-cells = <0>; |
| 51 | reg = <0x900b0024 0x4>; |
| 52 | clocks = <&base_clk>; |
| 53 | }; |
| 54 | |
| 55 | apb_pclk: apb_pclk { |
| 56 | #clock-cells = <0>; |
| 57 | compatible = "fixed-factor-clock"; |
| 58 | clock-div = <2>; |
| 59 | clock-mult = <1>; |
| 60 | clocks = <&ahb_clk>; |
| 61 | }; |
| 62 | |
| 63 | usb_phy: usb_phy { |
| 64 | compatible = "usb-nop-xceiv"; |
| 65 | #phy-cells = <0>; |
| 66 | }; |
| 67 | |
| 68 | vbus_reg: vbus_reg { |
| 69 | compatible = "regulator-fixed"; |
| 70 | |
| 71 | regulator-name = "USB VBUS output"; |
| 72 | |
| 73 | regulator-min-microvolt = <5000000>; |
| 74 | regulator-max-microvolt = <5000000>; |
| 75 | }; |
| 76 | |
| 77 | ahb { |
| 78 | compatible = "simple-bus"; |
| 79 | #address-cells = <1>; |
| 80 | #size-cells = <1>; |
| 81 | ranges; |
| 82 | |
| 83 | spi: spi@a9000000 { |
| 84 | reg = <0xa9000000 0x1000>; |
| 85 | }; |
| 86 | |
| 87 | usb0: usb@b0000000 { |
| 88 | compatible = "lsi,zevio-usb"; |
| 89 | reg = <0xb0000000 0x1000>; |
| 90 | interrupts = <8>; |
| 91 | |
| 92 | usb-phy = <&usb_phy>; |
| 93 | vbus-supply = <&vbus_reg>; |
| 94 | }; |
| 95 | |
| 96 | usb1: usb@b4000000 { |
| 97 | reg = <0xb4000000 0x1000>; |
| 98 | interrupts = <9>; |
| 99 | status = "disabled"; |
| 100 | }; |
| 101 | |
| 102 | lcd: lcd@c0000000 { |
| 103 | compatible = "arm,pl111", "arm,primecell"; |
| 104 | reg = <0xc0000000 0x1000>; |
| 105 | interrupts = <21>; |
| 106 | |
| 107 | /* |
| 108 | * We assume the same clock is fed to APB and CLCDCLK. |
| 109 | * There is some code to scale the clock down by a factor |
| 110 | * 48 for the display so likely the frequency to the |
| 111 | * display is 1MHz and the CLCDCLK is 48 MHz. |
| 112 | */ |
| 113 | clocks = <&apb_pclk>, <&apb_pclk>; |
| 114 | clock-names = "clcdclk", "apb_pclk"; |
| 115 | }; |
| 116 | |
| 117 | adc: adc@c4000000 { |
| 118 | reg = <0xc4000000 0x1000>; |
| 119 | interrupts = <11>; |
| 120 | }; |
| 121 | |
| 122 | tdes: crypto@c8010000 { |
| 123 | reg = <0xc8010000 0x1000>; |
| 124 | }; |
| 125 | |
| 126 | sha256: crypto@cc000000 { |
| 127 | reg = <0xcc000000 0x1000>; |
| 128 | }; |
| 129 | |
| 130 | apb@90000000 { |
| 131 | compatible = "simple-bus"; |
| 132 | #address-cells = <1>; |
| 133 | #size-cells = <1>; |
| 134 | clock-ranges; |
| 135 | ranges; |
| 136 | |
| 137 | gpio: gpio@90000000 { |
| 138 | compatible = "lsi,zevio-gpio"; |
| 139 | reg = <0x90000000 0x1000>; |
| 140 | interrupts = <7>; |
| 141 | gpio-controller; |
| 142 | #gpio-cells = <2>; |
| 143 | }; |
| 144 | |
| 145 | fast_timer: timer@90010000 { |
| 146 | reg = <0x90010000 0x1000>; |
| 147 | interrupts = <17>; |
| 148 | }; |
| 149 | |
| 150 | uart: serial@90020000 { |
| 151 | reg = <0x90020000 0x1000>; |
| 152 | interrupts = <1>; |
| 153 | }; |
| 154 | |
| 155 | timer0: timer@900c0000 { |
| 156 | reg = <0x900c0000 0x1000>; |
| 157 | clocks = <&timer_clk>, <&timer_clk>, |
| 158 | <&timer_clk>; |
| 159 | clock-names = "timer0clk", "timer1clk", |
| 160 | "apb_pclk"; |
| 161 | }; |
| 162 | |
| 163 | timer1: timer@900d0000 { |
| 164 | reg = <0x900d0000 0x1000>; |
| 165 | interrupts = <19>; |
| 166 | clocks = <&timer_clk>, <&timer_clk>, |
| 167 | <&timer_clk>; |
| 168 | clock-names = "timer0clk", "timer1clk", |
| 169 | "apb_pclk"; |
| 170 | }; |
| 171 | |
| 172 | watchdog: watchdog@90060000 { |
| 173 | compatible = "arm,primecell"; |
| 174 | reg = <0x90060000 0x1000>; |
| 175 | interrupts = <3>; |
| 176 | }; |
| 177 | |
| 178 | rtc: rtc@90090000 { |
| 179 | reg = <0x90090000 0x1000>; |
| 180 | interrupts = <4>; |
| 181 | }; |
| 182 | |
| 183 | misc: misc@900a0000 { |
| 184 | compatible = "ti,nspire-misc", "syscon", "simple-mfd"; |
| 185 | reg = <0x900a0000 0x1000>; |
| 186 | |
| 187 | reboot { |
| 188 | compatible = "syscon-reboot"; |
| 189 | offset = <0x08>; |
| 190 | value = <0x02>; |
| 191 | }; |
| 192 | }; |
| 193 | |
| 194 | pwr: pwr@900b0000 { |
| 195 | reg = <0x900b0000 0x1000>; |
| 196 | interrupts = <15>; |
| 197 | }; |
| 198 | |
| 199 | keypad: input@900e0000 { |
| 200 | compatible = "ti,nspire-keypad"; |
| 201 | reg = <0x900e0000 0x1000>; |
| 202 | interrupts = <16>; |
| 203 | |
| 204 | scan-interval = <1000>; |
| 205 | row-delay = <200>; |
| 206 | |
| 207 | clocks = <&apb_pclk>; |
| 208 | }; |
| 209 | |
| 210 | contrast: contrast@900f0000 { |
| 211 | reg = <0x900f0000 0x1000>; |
| 212 | }; |
| 213 | |
| 214 | led: led@90110000 { |
| 215 | reg = <0x90110000 0x1000>; |
| 216 | }; |
| 217 | }; |
| 218 | }; |
| 219 | }; |