| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: StarFive JH7110 SYS Pin Controller |
| 8 | |
| 9 | description: | |
| 10 | Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. |
| 11 | |
| 12 | Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO63 |
| 13 | can be multiplexed and have configurable bias, drive strength, |
| 14 | schmitt trigger etc. |
| 15 | Some peripherals have their I/O go through the 64 "GPIOs". This also |
| 16 | includes a number of other UARTs, I2Cs, SPIs, PWMs etc. |
| 17 | All these peripherals are connected to all 64 GPIOs such that |
| 18 | any GPIO can be set up to be controlled by any of the peripherals. |
| 19 | |
| 20 | maintainers: |
| 21 | - Jianlong Huang <jianlong.huang@starfivetech.com> |
| 22 | |
| 23 | properties: |
| 24 | compatible: |
| 25 | const: starfive,jh7110-sys-pinctrl |
| 26 | |
| 27 | reg: |
| 28 | maxItems: 1 |
| 29 | |
| 30 | clocks: |
| 31 | maxItems: 1 |
| 32 | |
| 33 | resets: |
| 34 | maxItems: 1 |
| 35 | |
| 36 | interrupts: |
| 37 | maxItems: 1 |
| 38 | |
| 39 | interrupt-controller: true |
| 40 | |
| 41 | '#interrupt-cells': |
| 42 | const: 2 |
| 43 | |
| 44 | gpio-controller: true |
| 45 | |
| 46 | '#gpio-cells': |
| 47 | const: 2 |
| 48 | |
| 49 | patternProperties: |
| 50 | '-[0-9]+$': |
| 51 | type: object |
| 52 | additionalProperties: false |
| 53 | patternProperties: |
| 54 | '-pins$': |
| 55 | type: object |
| 56 | description: | |
| 57 | A pinctrl node should contain at least one subnode representing the |
| 58 | pinctrl groups available on the machine. Each subnode will list the |
| 59 | pins it needs, and how they should be configured, with regard to |
| 60 | muxer configuration, bias, input enable/disable, input schmitt |
| 61 | trigger enable/disable, slew-rate and drive strength. |
| 62 | allOf: |
| 63 | - $ref: /schemas/pinctrl/pincfg-node.yaml |
| 64 | - $ref: /schemas/pinctrl/pinmux-node.yaml |
| 65 | additionalProperties: false |
| 66 | |
| 67 | properties: |
| 68 | pinmux: |
| 69 | description: | |
| 70 | The list of GPIOs and their mux settings that properties in the |
| 71 | node apply to. This should be set using the GPIOMUX or PINMUX |
| 72 | macros. |
| 73 | |
| 74 | bias-disable: true |
| 75 | |
| 76 | bias-pull-up: |
| 77 | type: boolean |
| 78 | |
| 79 | bias-pull-down: |
| 80 | type: boolean |
| 81 | |
| 82 | drive-strength: |
| 83 | enum: [ 2, 4, 8, 12 ] |
| 84 | |
| 85 | input-enable: true |
| 86 | |
| 87 | input-disable: true |
| 88 | |
| 89 | input-schmitt-enable: true |
| 90 | |
| 91 | input-schmitt-disable: true |
| 92 | |
| 93 | slew-rate: |
| 94 | maximum: 1 |
| 95 | |
| 96 | required: |
| 97 | - compatible |
| 98 | - reg |
| 99 | - clocks |
| 100 | - interrupts |
| 101 | - interrupt-controller |
| 102 | - '#interrupt-cells' |
| 103 | - gpio-controller |
| 104 | - '#gpio-cells' |
| 105 | |
| 106 | additionalProperties: false |
| 107 | |
| 108 | examples: |
| 109 | - | |
| 110 | pinctrl@13040000 { |
| 111 | compatible = "starfive,jh7110-sys-pinctrl"; |
| 112 | reg = <0x13040000 0x10000>; |
| 113 | clocks = <&syscrg 112>; |
| 114 | resets = <&syscrg 2>; |
| 115 | interrupts = <86>; |
| 116 | interrupt-controller; |
| 117 | #interrupt-cells = <2>; |
| 118 | gpio-controller; |
| 119 | #gpio-cells = <2>; |
| 120 | |
| 121 | uart0-0 { |
| 122 | tx-pins { |
| 123 | pinmux = <0xff140005>; |
| 124 | bias-disable; |
| 125 | drive-strength = <12>; |
| 126 | input-disable; |
| 127 | input-schmitt-disable; |
| 128 | slew-rate = <0>; |
| 129 | }; |
| 130 | |
| 131 | rx-pins { |
| 132 | pinmux = <0x0E000406>; |
| 133 | bias-pull-up; |
| 134 | drive-strength = <2>; |
| 135 | input-enable; |
| 136 | input-schmitt-enable; |
| 137 | slew-rate = <0>; |
| 138 | }; |
| 139 | }; |
| 140 | }; |
| 141 | |
| 142 | ... |