| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | * Marvell Orion SoC pinctrl driver for mpp |
| 2 | |
| 3 | Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding |
| 4 | part and usage. |
| 5 | |
| 6 | Required properties: |
| 7 | - compatible: "marvell,88f5181-pinctrl", |
| 8 | "marvell,88f5181l-pinctrl", |
| 9 | "marvell,88f5182-pinctrl", |
| 10 | "marvell,88f5281-pinctrl" |
| 11 | |
| 12 | - reg: two register areas, the first one describing the first two |
| 13 | contiguous MPP registers, and the second one describing the single |
| 14 | final MPP register, separated from the previous one. |
| 15 | |
| 16 | Available mpp pins/groups and functions: |
| 17 | Note: brackets (x) are not part of the mpp name for marvell,function and given |
| 18 | only for more detailed description in this document. |
| 19 | |
| 20 | * Marvell Orion 88f5181l |
| 21 | |
| 22 | name pins functions |
| 23 | ================================================================================ |
| 24 | mpp0 0 pcie(rstout), pci(req2), gpio |
| 25 | mpp1 1 gpio, pci(gnt2) |
| 26 | mpp2 2 gpio, pci(req3), pci-1(pme) |
| 27 | mpp3 3 gpio, pci(gnt3) |
| 28 | mpp4 4 gpio, pci(req4) |
| 29 | mpp5 5 gpio, pci(gnt4) |
| 30 | mpp6 6 gpio, pci(req5), pci-1(clk) |
| 31 | mpp7 7 gpio, pci(gnt5), pci-1(clk) |
| 32 | mpp8 8 gpio, ge(col) |
| 33 | mpp9 9 gpio, ge(rxerr) |
| 34 | mpp10 10 gpio, ge(crs) |
| 35 | mpp11 11 gpio, ge(txerr) |
| 36 | mpp12 12 gpio, ge(txd4) |
| 37 | mpp13 13 gpio, ge(txd5) |
| 38 | mpp14 14 gpio, ge(txd6) |
| 39 | mpp15 15 gpio, ge(txd7) |
| 40 | mpp16 16 ge(rxd4) |
| 41 | mpp17 17 ge(rxd5) |
| 42 | mpp18 18 ge(rxd6) |
| 43 | mpp19 19 ge(rxd7) |
| 44 | |
| 45 | * Marvell Orion 88f5182 |
| 46 | |
| 47 | name pins functions |
| 48 | ================================================================================ |
| 49 | mpp0 0 pcie(rstout), pci(req2), gpio |
| 50 | mpp1 1 gpio, pci(gnt2) |
| 51 | mpp2 2 gpio, pci(req3), pci-1(pme) |
| 52 | mpp3 3 gpio, pci(gnt3) |
| 53 | mpp4 4 gpio, pci(req4), bootnand(re), sata0(prsnt) |
| 54 | mpp5 5 gpio, pci(gnt4), bootnand(we), sata1(prsnt) |
| 55 | mpp6 6 gpio, pci(req5), nand(re0), sata0(act) |
| 56 | mpp7 7 gpio, pci(gnt5), nand(we0), sata1(act) |
| 57 | mpp8 8 gpio, ge(col) |
| 58 | mpp9 9 gpio, ge(rxerr) |
| 59 | mpp10 10 gpio, ge(crs) |
| 60 | mpp11 11 gpio, ge(txerr) |
| 61 | mpp12 12 gpio, ge(txd4), nand(re1), sata0(ledprsnt) |
| 62 | mpp13 13 gpio, ge(txd5), nand(we1), sata1(ledprsnt) |
| 63 | mpp14 14 gpio, ge(txd6), nand(re2), sata0(ledact) |
| 64 | mpp15 15 gpio, ge(txd7), nand(we2), sata1(ledact) |
| 65 | mpp16 16 uart1(rxd), ge(rxd4), gpio |
| 66 | mpp17 17 uart1(txd), ge(rxd5), gpio |
| 67 | mpp18 18 uart1(cts), ge(rxd6), gpio |
| 68 | mpp19 19 uart1(rts), ge(rxd7), gpio |
| 69 | |
| 70 | * Marvell Orion 88f5281 |
| 71 | |
| 72 | name pins functions |
| 73 | ================================================================================ |
| 74 | mpp0 0 pcie(rstout), pci(req2), gpio |
| 75 | mpp1 1 gpio, pci(gnt2) |
| 76 | mpp2 2 gpio, pci(req3), pci(pme) |
| 77 | mpp3 3 gpio, pci(gnt3) |
| 78 | mpp4 4 gpio, pci(req4), bootnand(re) |
| 79 | mpp5 5 gpio, pci(gnt4), bootnand(we) |
| 80 | mpp6 6 gpio, pci(req5), nand(re0) |
| 81 | mpp7 7 gpio, pci(gnt5), nand(we0) |
| 82 | mpp8 8 gpio, ge(col) |
| 83 | mpp9 9 gpio, ge(rxerr) |
| 84 | mpp10 10 gpio, ge(crs) |
| 85 | mpp11 11 gpio, ge(txerr) |
| 86 | mpp12 12 gpio, ge(txd4), nand(re1) |
| 87 | mpp13 13 gpio, ge(txd5), nand(we1) |
| 88 | mpp14 14 gpio, ge(txd6), nand(re2) |
| 89 | mpp15 15 gpio, ge(txd7), nand(we2) |
| 90 | mpp16 16 uart1(rxd), ge(rxd4) |
| 91 | mpp17 17 uart1(txd), ge(rxd5) |
| 92 | mpp18 18 uart1(cts), ge(rxd6) |
| 93 | mpp19 19 uart1(rts), ge(rxd7) |