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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/crypto/st,stm32-hash.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: STMicroelectronics STM32 HASH
8
9description: The STM32 HASH block is built on the HASH block found in
10 the STn8820 SoC introduced in 2007, and subsequently used in the U8500
11 SoC in 2010.
12
13maintainers:
14 - Lionel Debieve <lionel.debieve@foss.st.com>
15
16properties:
17 compatible:
18 enum:
19 - st,stn8820-hash
20 - stericsson,ux500-hash
21 - st,stm32f456-hash
22 - st,stm32f756-hash
23 - st,stm32mp13-hash
24
25 reg:
26 maxItems: 1
27
28 clocks:
29 maxItems: 1
30
31 interrupts:
32 maxItems: 1
33
34 resets:
35 maxItems: 1
36
37 dmas:
38 maxItems: 1
39
40 dma-names:
41 items:
42 - const: in
43
44 dma-maxburst:
45 description: Set number of maximum dma burst supported
46 $ref: /schemas/types.yaml#/definitions/uint32
47 minimum: 0
48 maximum: 2
49 default: 0
50
51 power-domains:
52 maxItems: 1
53
Tom Rini762f85b2024-07-20 11:15:10 -060054 access-controllers:
55 minItems: 1
56 maxItems: 2
57
Tom Rini53633a82024-02-29 12:33:36 -050058required:
59 - compatible
60 - reg
61 - clocks
62
63allOf:
64 - if:
65 properties:
66 compatible:
67 items:
68 const: stericsson,ux500-hash
69 then:
70 properties:
71 interrupts: false
72 else:
73 required:
74 - interrupts
75
76additionalProperties: false
77
78examples:
79 - |
80 #include <dt-bindings/interrupt-controller/arm-gic.h>
81 #include <dt-bindings/clock/stm32mp1-clks.h>
82 #include <dt-bindings/reset/stm32mp1-resets.h>
83 hash@54002000 {
84 compatible = "st,stm32f756-hash";
85 reg = <0x54002000 0x400>;
86 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
87 clocks = <&rcc HASH1>;
88 resets = <&rcc HASH1_R>;
89 dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
90 dma-names = "in";
91 dma-maxburst = <2>;
92 };
93
94...