Peter Crosthwaite | 9d7740a | 2014-08-28 21:16:39 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Digilent ZYBO board DTS |
| 3 | * |
Michal Simek | e2612e1 | 2015-07-22 11:12:10 +0200 | [diff] [blame] | 4 | * Copyright (C) 2011 - 2015 Xilinx |
| 5 | * Copyright (C) 2012 National Instruments Corp. |
Peter Crosthwaite | 9d7740a | 2014-08-28 21:16:39 +1000 | [diff] [blame] | 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | /dts-v1/; |
| 10 | #include "zynq-7000.dtsi" |
| 11 | |
| 12 | / { |
Michal Simek | e2612e1 | 2015-07-22 11:12:10 +0200 | [diff] [blame] | 13 | model = "Zynq ZYBO Development Board"; |
| 14 | compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; |
Peter Crosthwaite | 9d7740a | 2014-08-28 21:16:39 +1000 | [diff] [blame] | 15 | |
| 16 | aliases { |
Michal Simek | e2612e1 | 2015-07-22 11:12:10 +0200 | [diff] [blame] | 17 | ethernet0 = &gem0; |
Peter Crosthwaite | 9d7740a | 2014-08-28 21:16:39 +1000 | [diff] [blame] | 18 | serial0 = &uart1; |
| 19 | }; |
| 20 | |
| 21 | memory { |
| 22 | device_type = "memory"; |
Michal Simek | e2612e1 | 2015-07-22 11:12:10 +0200 | [diff] [blame] | 23 | reg = <0x0 0x20000000>; |
Peter Crosthwaite | 9d7740a | 2014-08-28 21:16:39 +1000 | [diff] [blame] | 24 | }; |
Michal Simek | e2612e1 | 2015-07-22 11:12:10 +0200 | [diff] [blame] | 25 | |
| 26 | chosen { |
| 27 | bootargs = "earlyprintk"; |
| 28 | stdout-path = "serial0:115200n8"; |
| 29 | }; |
| 30 | |
| 31 | }; |
| 32 | |
| 33 | &clkc { |
| 34 | ps-clk-frequency = <50000000>; |
| 35 | }; |
| 36 | |
| 37 | &gem0 { |
| 38 | status = "okay"; |
| 39 | phy-mode = "rgmii-id"; |
| 40 | phy-handle = <ðernet_phy>; |
| 41 | |
| 42 | ethernet_phy: ethernet-phy@0 { |
| 43 | reg = <0>; |
| 44 | }; |
| 45 | }; |
| 46 | |
| 47 | &sdhci0 { |
| 48 | status = "okay"; |
| 49 | }; |
| 50 | |
| 51 | &uart1 { |
| 52 | status = "okay"; |
Peter Crosthwaite | 9d7740a | 2014-08-28 21:16:39 +1000 | [diff] [blame] | 53 | }; |