blob: 07535a6b7d3457ebb2850ff18851a7d80853f009 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
5
Simon Glassb2c1cac2014-02-26 15:59:21 -07006/ {
7 model = "sandbox";
8 compatible = "sandbox";
9 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060010 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070011
Simon Glassfef72b72014-07-23 06:55:03 -060012 aliases {
13 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -060014 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -070015 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -060016 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060017 gpio1 = &gpio_a;
18 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010019 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070020 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060021 mmc0 = "/mmc0";
22 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070023 pci0 = &pci0;
24 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070025 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020026 remoteproc0 = &rproc_1;
27 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060028 rtc0 = &rtc_0;
29 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060030 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020031 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070032 testbus3 = "/some-bus";
33 testfdt0 = "/some-bus/c-test@0";
34 testfdt1 = "/some-bus/c-test@1";
35 testfdt3 = "/b-test";
36 testfdt5 = "/some-bus/c-test@5";
37 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020038 fdt-dummy0 = "/translation-test@8000/dev@0,0";
39 fdt-dummy1 = "/translation-test@8000/dev@1,100";
40 fdt-dummy2 = "/translation-test@8000/dev@2,200";
41 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060042 usb0 = &usb_0;
43 usb1 = &usb_1;
44 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020045 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020046 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060047 };
48
Simon Glassed96cde2018-12-10 10:37:33 -070049 audio: audio-codec {
50 compatible = "sandbox,audio-codec";
51 #sound-dai-cells = <1>;
52 };
53
Simon Glassc953aaf2018-12-10 10:37:34 -070054 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -060055 reg = <0 0>;
56 compatible = "google,cros-ec-sandbox";
57
58 /*
59 * This describes the flash memory within the EC. Note
60 * that the STM32L flash erases to 0, not 0xff.
61 */
62 flash {
63 image-pos = <0x08000000>;
64 size = <0x20000>;
65 erase-value = <0>;
66
67 /* Information for sandbox */
68 ro {
69 image-pos = <0>;
70 size = <0xf000>;
71 };
72 wp-ro {
73 image-pos = <0xf000>;
74 size = <0x1000>;
75 };
76 rw {
77 image-pos = <0x10000>;
78 size = <0x10000>;
79 };
80 };
81 };
82
Yannick Fertré9712c822019-10-07 15:29:05 +020083 dsi_host: dsi_host {
84 compatible = "sandbox,dsi-host";
85 };
86
Simon Glassb2c1cac2014-02-26 15:59:21 -070087 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -060088 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070089 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -060090 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070091 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -060092 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +010093 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
94 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -070095 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +010096 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
97 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
98 <&gpio_b 7 GPIO_IN 3 2 1>,
99 <&gpio_b 8 GPIO_OUT 3 2 1>,
100 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100101 test3-gpios =
102 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
103 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
104 <&gpio_c 2 GPIO_OUT>,
105 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
106 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200107 <&gpio_c 5 GPIO_IN>,
108 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
109 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Simon Glass6df01f92018-12-10 10:37:37 -0700110 int-value = <1234>;
111 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200112 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200113 int-array = <5678 9123 4567>;
Simon Glass515dcff2020-02-06 09:55:00 -0700114 interrupts-extended = <&irq 3 0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700115 };
116
117 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600118 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700119 compatible = "not,compatible";
120 };
121
122 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600123 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700124 };
125
Simon Glass5620cf82018-10-01 12:22:40 -0600126 backlight: backlight {
127 compatible = "pwm-backlight";
128 enable-gpios = <&gpio_a 1>;
129 power-supply = <&ldo_1>;
130 pwms = <&pwm 0 1000>;
131 default-brightness-level = <5>;
132 brightness-levels = <0 16 32 64 128 170 202 234 255>;
133 };
134
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200135 bind-test {
136 bind-test-child1 {
137 compatible = "sandbox,phy";
138 #phy-cells = <1>;
139 };
140
141 bind-test-child2 {
142 compatible = "simple-bus";
143 };
144 };
145
Simon Glassb2c1cac2014-02-26 15:59:21 -0700146 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600147 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700148 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600149 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700150 ping-add = <3>;
151 };
152
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200153 phy_provider0: gen_phy@0 {
154 compatible = "sandbox,phy";
155 #phy-cells = <1>;
156 };
157
158 phy_provider1: gen_phy@1 {
159 compatible = "sandbox,phy";
160 #phy-cells = <0>;
161 broken;
162 };
163
developer71092972020-05-02 11:35:12 +0200164 phy_provider2: gen_phy@2 {
165 compatible = "sandbox,phy";
166 #phy-cells = <0>;
167 };
168
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200169 gen_phy_user: gen_phy_user {
170 compatible = "simple-bus";
171 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
172 phy-names = "phy1", "phy2", "phy3";
173 };
174
developer71092972020-05-02 11:35:12 +0200175 gen_phy_user1: gen_phy_user1 {
176 compatible = "simple-bus";
177 phys = <&phy_provider0 0>, <&phy_provider2>;
178 phy-names = "phy1", "phy2";
179 };
180
Simon Glassb2c1cac2014-02-26 15:59:21 -0700181 some-bus {
182 #address-cells = <1>;
183 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600184 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600185 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600186 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700187 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600188 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700189 compatible = "denx,u-boot-fdt-test";
190 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600191 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700192 ping-add = <5>;
193 };
Simon Glass40717422014-07-23 06:55:18 -0600194 c-test@0 {
195 compatible = "denx,u-boot-fdt-test";
196 reg = <0>;
197 ping-expect = <6>;
198 ping-add = <6>;
199 };
200 c-test@1 {
201 compatible = "denx,u-boot-fdt-test";
202 reg = <1>;
203 ping-expect = <7>;
204 ping-add = <7>;
205 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700206 };
207
208 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600209 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600210 ping-expect = <6>;
211 ping-add = <6>;
212 compatible = "google,another-fdt-test";
213 };
214
215 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600216 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600217 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700218 ping-add = <6>;
219 compatible = "google,another-fdt-test";
220 };
221
Simon Glass0ccb0972015-01-25 08:27:05 -0700222 f-test {
223 compatible = "denx,u-boot-fdt-test";
224 };
225
226 g-test {
227 compatible = "denx,u-boot-fdt-test";
228 };
229
Bin Mengd9d24782018-10-10 22:07:01 -0700230 h-test {
231 compatible = "denx,u-boot-fdt-test1";
232 };
233
developercf8bc132020-05-02 11:35:10 +0200234 i-test {
235 compatible = "mediatek,u-boot-fdt-test";
236 #address-cells = <1>;
237 #size-cells = <0>;
238
239 subnode@0 {
240 reg = <0>;
241 };
242
243 subnode@1 {
244 reg = <1>;
245 };
246
247 subnode@2 {
248 reg = <2>;
249 };
250 };
251
Simon Glass204675c2019-12-29 21:19:25 -0700252 devres-test {
253 compatible = "denx,u-boot-devres-test";
254 };
255
Simon Glass2d67fdf2020-04-08 16:57:34 -0600256 acpi-test {
257 compatible = "denx,u-boot-acpi-test";
258 };
259
Simon Glass17968c32020-04-26 09:19:46 -0600260 acpi-test2 {
261 compatible = "denx,u-boot-acpi-test";
262 };
263
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200264 clocks {
265 clk_fixed: clk-fixed {
266 compatible = "fixed-clock";
267 #clock-cells = <0>;
268 clock-frequency = <1234>;
269 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000270
271 clk_fixed_factor: clk-fixed-factor {
272 compatible = "fixed-factor-clock";
273 #clock-cells = <0>;
274 clock-div = <3>;
275 clock-mult = <2>;
276 clocks = <&clk_fixed>;
277 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200278
279 osc {
280 compatible = "fixed-clock";
281 #clock-cells = <0>;
282 clock-frequency = <20000000>;
283 };
Stephen Warrena9622432016-06-17 09:44:00 -0600284 };
285
286 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600287 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600288 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200289 assigned-clocks = <&clk_sandbox 3>;
290 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600291 };
292
293 clk-test {
294 compatible = "sandbox,clk-test";
295 clocks = <&clk_fixed>,
296 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200297 <&clk_sandbox 0>,
298 <&clk_sandbox 3>,
299 <&clk_sandbox 2>;
300 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600301 };
302
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200303 ccf: clk-ccf {
304 compatible = "sandbox,clk-ccf";
305 };
306
Simon Glass5b968632015-05-22 15:42:15 -0600307 eth@10002000 {
308 compatible = "sandbox,eth";
309 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500310 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600311 };
312
313 eth_5: eth@10003000 {
314 compatible = "sandbox,eth";
315 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500316 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600317 };
318
Bin Meng04a11cb2015-08-27 22:25:53 -0700319 eth_3: sbe5 {
320 compatible = "sandbox,eth";
321 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500322 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700323 };
324
Simon Glass5b968632015-05-22 15:42:15 -0600325 eth@10004000 {
326 compatible = "sandbox,eth";
327 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500328 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600329 };
330
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700331 firmware {
332 sandbox_firmware: sandbox-firmware {
333 compatible = "sandbox,firmware";
334 };
335 };
336
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100337 pinctrl-gpio {
338 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700339
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100340 gpio_a: base-gpios {
341 compatible = "sandbox,gpio";
342 gpio-controller;
343 #gpio-cells = <1>;
344 gpio-bank-name = "a";
345 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200346 hog_input_active_low {
347 gpio-hog;
348 input;
349 gpios = <0 GPIO_ACTIVE_LOW>;
350 };
351 hog_input_active_high {
352 gpio-hog;
353 input;
354 gpios = <1 GPIO_ACTIVE_HIGH>;
355 };
356 hog_output_low {
357 gpio-hog;
358 output-low;
359 gpios = <2 GPIO_ACTIVE_HIGH>;
360 };
361 hog_output_high {
362 gpio-hog;
363 output-high;
364 gpios = <3 GPIO_ACTIVE_HIGH>;
365 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100366 };
367
368 gpio_b: extra-gpios {
369 compatible = "sandbox,gpio";
370 gpio-controller;
371 #gpio-cells = <5>;
372 gpio-bank-name = "b";
373 sandbox,gpio-count = <10>;
374 };
Simon Glass25348a42014-10-13 23:42:11 -0600375
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100376 gpio_c: pinmux-gpios {
377 compatible = "sandbox,gpio";
378 gpio-controller;
379 #gpio-cells = <2>;
380 gpio-bank-name = "c";
381 sandbox,gpio-count = <10>;
382 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100383 };
384
Simon Glass7df766e2014-12-10 08:55:55 -0700385 i2c@0 {
386 #address-cells = <1>;
387 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600388 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700389 compatible = "sandbox,i2c";
390 clock-frequency = <100000>;
391 eeprom@2c {
392 reg = <0x2c>;
393 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700394 sandbox,emul = <&emul_eeprom>;
Simon Glass7df766e2014-12-10 08:55:55 -0700395 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200396
Simon Glass336b2952015-05-22 15:42:17 -0600397 rtc_0: rtc@43 {
398 reg = <0x43>;
399 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700400 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600401 };
402
403 rtc_1: rtc@61 {
404 reg = <0x61>;
405 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700406 sandbox,emul = <&emul1>;
407 };
408
409 i2c_emul: emul {
410 reg = <0xff>;
411 compatible = "sandbox,i2c-emul-parent";
412 emul_eeprom: emul-eeprom {
413 compatible = "sandbox,i2c-eeprom";
414 sandbox,filename = "i2c.bin";
415 sandbox,size = <256>;
416 };
417 emul0: emul0 {
418 compatible = "sandbox,i2c-rtc";
419 };
420 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600421 compatible = "sandbox,i2c-rtc";
422 };
423 };
424
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200425 sandbox_pmic: sandbox_pmic {
426 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700427 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200428 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200429
430 mc34708: pmic@41 {
431 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700432 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200433 };
Simon Glass7df766e2014-12-10 08:55:55 -0700434 };
435
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100436 bootcount@0 {
437 compatible = "u-boot,bootcount-rtc";
438 rtc = <&rtc_1>;
439 offset = <0x13>;
440 };
441
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100442 adc@0 {
443 compatible = "sandbox,adc";
444 vdd-supply = <&buck2>;
445 vss-microvolts = <0>;
446 };
447
Simon Glass515dcff2020-02-06 09:55:00 -0700448 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700449 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700450 interrupt-controller;
451 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700452 };
453
Simon Glass90b6fef2016-01-18 19:52:26 -0700454 lcd {
455 u-boot,dm-pre-reloc;
456 compatible = "sandbox,lcd-sdl";
457 xres = <1366>;
458 yres = <768>;
459 };
460
Simon Glassd783eb32015-07-06 12:54:34 -0600461 leds {
462 compatible = "gpio-leds";
463
464 iracibble {
465 gpios = <&gpio_a 1 0>;
466 label = "sandbox:red";
467 };
468
469 martinet {
470 gpios = <&gpio_a 2 0>;
471 label = "sandbox:green";
472 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200473
474 default_on {
475 gpios = <&gpio_a 5 0>;
476 label = "sandbox:default_on";
477 default-state = "on";
478 };
479
480 default_off {
481 gpios = <&gpio_a 6 0>;
482 label = "sandbox:default_off";
483 default-state = "off";
484 };
Simon Glassd783eb32015-07-06 12:54:34 -0600485 };
486
Stephen Warren62f2c902016-05-16 17:41:37 -0600487 mbox: mbox {
488 compatible = "sandbox,mbox";
489 #mbox-cells = <1>;
490 };
491
492 mbox-test {
493 compatible = "sandbox,mbox-test";
494 mboxes = <&mbox 100>, <&mbox 1>;
495 mbox-names = "other", "test";
496 };
497
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900498 cpus {
499 cpu-test1 {
500 compatible = "sandbox,cpu_sandbox";
501 u-boot,dm-pre-reloc;
502 };
Mario Sixdea5df72018-08-06 10:23:44 +0200503
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900504 cpu-test2 {
505 compatible = "sandbox,cpu_sandbox";
506 u-boot,dm-pre-reloc;
507 };
Mario Sixdea5df72018-08-06 10:23:44 +0200508
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900509 cpu-test3 {
510 compatible = "sandbox,cpu_sandbox";
511 u-boot,dm-pre-reloc;
512 };
Mario Sixdea5df72018-08-06 10:23:44 +0200513 };
514
Simon Glassc953aaf2018-12-10 10:37:34 -0700515 i2s: i2s {
516 compatible = "sandbox,i2s";
517 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700518 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700519 };
520
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200521 nop-test_0 {
522 compatible = "sandbox,nop_sandbox1";
523 nop-test_1 {
524 compatible = "sandbox,nop_sandbox2";
525 bind = "True";
526 };
527 nop-test_2 {
528 compatible = "sandbox,nop_sandbox2";
529 bind = "False";
530 };
531 };
532
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200533 misc-test {
534 compatible = "sandbox,misc_sandbox";
535 };
536
Simon Glasse4fef742017-04-23 20:02:07 -0600537 mmc2 {
538 compatible = "sandbox,mmc";
539 };
540
541 mmc1 {
542 compatible = "sandbox,mmc";
543 };
544
545 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600546 compatible = "sandbox,mmc";
547 };
548
Simon Glass53a68b32019-02-16 20:24:50 -0700549 pch {
550 compatible = "sandbox,pch";
551 };
552
Tom Rini4a3ca482020-02-11 12:41:23 -0500553 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700554 compatible = "sandbox,pci";
555 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500556 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700557 #address-cells = <3>;
558 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600559 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700560 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700561 pci@0,0 {
562 compatible = "pci-generic";
563 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600564 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700565 };
Alex Margineanf1274432019-06-07 11:24:24 +0300566 pci@1,0 {
567 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600568 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
569 reg = <0x02000814 0 0 0 0
570 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600571 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300572 };
Simon Glass937bb472019-12-06 21:41:57 -0700573 p2sb-pci@2,0 {
574 compatible = "sandbox,p2sb";
575 reg = <0x02001010 0 0 0 0>;
576 sandbox,emul = <&p2sb_emul>;
577
578 adder {
579 intel,p2sb-port-id = <3>;
580 compatible = "sandbox,adder";
581 };
582 };
Simon Glass8c501022019-12-06 21:41:54 -0700583 pci@1e,0 {
584 compatible = "sandbox,pmc";
585 reg = <0xf000 0 0 0 0>;
586 sandbox,emul = <&pmc_emul1e>;
587 acpi-base = <0x400>;
588 gpe0-dwx-mask = <0xf>;
589 gpe0-dwx-shift-base = <4>;
590 gpe0-dw = <6 7 9>;
591 gpe0-sts = <0x20>;
592 gpe0-en = <0x30>;
593 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700594 pci@1f,0 {
595 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600596 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
597 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600598 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700599 };
600 };
601
Simon Glassb98ba4c2019-09-25 08:56:10 -0600602 pci-emul0 {
603 compatible = "sandbox,pci-emul-parent";
604 swap_case_emul0_0: emul0@0,0 {
605 compatible = "sandbox,swap-case";
606 };
607 swap_case_emul0_1: emul0@1,0 {
608 compatible = "sandbox,swap-case";
609 use-ea;
610 };
611 swap_case_emul0_1f: emul0@1f,0 {
612 compatible = "sandbox,swap-case";
613 };
Simon Glass937bb472019-12-06 21:41:57 -0700614 p2sb_emul: emul@2,0 {
615 compatible = "sandbox,p2sb-emul";
616 };
Simon Glass8c501022019-12-06 21:41:54 -0700617 pmc_emul1e: emul@1e,0 {
618 compatible = "sandbox,pmc-emul";
619 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600620 };
621
Tom Rini4a3ca482020-02-11 12:41:23 -0500622 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700623 compatible = "sandbox,pci";
624 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500625 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700626 #address-cells = <3>;
627 #size-cells = <2>;
628 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
629 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700630 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200631 0x0c 0x00 0x1234 0x5678
632 0x10 0x00 0x1234 0x5678>;
633 pci@10,0 {
634 reg = <0x8000 0 0 0 0>;
635 };
Bin Meng408e5902018-08-03 01:14:41 -0700636 };
637
Tom Rini4a3ca482020-02-11 12:41:23 -0500638 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700639 compatible = "sandbox,pci";
640 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500641 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700642 #address-cells = <3>;
643 #size-cells = <2>;
644 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
645 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
646 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
647 pci@1f,0 {
648 compatible = "pci-generic";
649 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600650 sandbox,emul = <&swap_case_emul2_1f>;
651 };
652 };
653
654 pci-emul2 {
655 compatible = "sandbox,pci-emul-parent";
656 swap_case_emul2_1f: emul2@1f,0 {
657 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700658 };
659 };
660
Ramon Friedc64f19b2019-04-27 11:15:23 +0300661 pci_ep: pci_ep {
662 compatible = "sandbox,pci_ep";
663 };
664
Simon Glass9c433fe2017-04-23 20:10:44 -0600665 probing {
666 compatible = "simple-bus";
667 test1 {
668 compatible = "denx,u-boot-probe-test";
669 };
670
671 test2 {
672 compatible = "denx,u-boot-probe-test";
673 };
674
675 test3 {
676 compatible = "denx,u-boot-probe-test";
677 };
678
679 test4 {
680 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100681 first-syscon = <&syscon0>;
682 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100683 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600684 };
685 };
686
Stephen Warren92c67fa2016-07-13 13:45:31 -0600687 pwrdom: power-domain {
688 compatible = "sandbox,power-domain";
689 #power-domain-cells = <1>;
690 };
691
692 power-domain-test {
693 compatible = "sandbox,power-domain-test";
694 power-domains = <&pwrdom 2>;
695 };
696
Simon Glass5620cf82018-10-01 12:22:40 -0600697 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600698 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600699 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600700 };
701
702 pwm2 {
703 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600704 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600705 };
706
Simon Glass3d355e62015-07-06 12:54:31 -0600707 ram {
708 compatible = "sandbox,ram";
709 };
710
Simon Glassd860f222015-07-06 12:54:29 -0600711 reset@0 {
712 compatible = "sandbox,warm-reset";
713 };
714
715 reset@1 {
716 compatible = "sandbox,reset";
717 };
718
Stephen Warren6488e642016-06-17 09:43:59 -0600719 resetc: reset-ctl {
720 compatible = "sandbox,reset-ctl";
721 #reset-cells = <1>;
722 };
723
724 reset-ctl-test {
725 compatible = "sandbox,reset-ctl-test";
726 resets = <&resetc 100>, <&resetc 2>;
727 reset-names = "other", "test";
728 };
729
Sughosh Ganu23e37512019-12-28 23:58:31 +0530730 rng {
731 compatible = "sandbox,sandbox-rng";
732 };
733
Nishanth Menonedf85812015-09-17 15:42:41 -0500734 rproc_1: rproc@1 {
735 compatible = "sandbox,test-processor";
736 remoteproc-name = "remoteproc-test-dev1";
737 };
738
739 rproc_2: rproc@2 {
740 compatible = "sandbox,test-processor";
741 internal-memory-mapped;
742 remoteproc-name = "remoteproc-test-dev2";
743 };
744
Simon Glass5620cf82018-10-01 12:22:40 -0600745 panel {
746 compatible = "simple-panel";
747 backlight = <&backlight 0 100>;
748 };
749
Ramon Fried26ed32e2018-07-02 02:57:59 +0300750 smem@0 {
751 compatible = "sandbox,smem";
752 };
753
Simon Glass76072ac2018-12-10 10:37:36 -0700754 sound {
755 compatible = "sandbox,sound";
756 cpu {
757 sound-dai = <&i2s 0>;
758 };
759
760 codec {
761 sound-dai = <&audio 0>;
762 };
763 };
764
Simon Glass25348a42014-10-13 23:42:11 -0600765 spi@0 {
766 #address-cells = <1>;
767 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600768 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600769 compatible = "sandbox,spi";
770 cs-gpios = <0>, <&gpio_a 0>;
771 spi.bin@0 {
772 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000773 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600774 spi-max-frequency = <40000000>;
775 sandbox,filename = "spi.bin";
776 };
777 };
778
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100779 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600780 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200781 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600782 };
783
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100784 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600785 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600786 reg = <0x20 5
787 0x28 6
788 0x30 7
789 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600790 };
791
Patrick Delaunayee010432019-03-07 09:57:13 +0100792 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900793 compatible = "simple-mfd", "syscon";
794 reg = <0x40 5
795 0x48 6
796 0x50 7
797 0x58 8>;
798 };
799
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800800 timer {
801 compatible = "sandbox,timer";
802 clock-frequency = <1000000>;
803 };
804
Miquel Raynal80938c12018-05-15 11:57:27 +0200805 tpm2 {
806 compatible = "sandbox,tpm2";
807 };
808
Simon Glass5b968632015-05-22 15:42:15 -0600809 uart0: serial {
810 compatible = "sandbox,serial";
811 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500812 };
813
Simon Glass31680482015-03-25 12:23:05 -0600814 usb_0: usb@0 {
815 compatible = "sandbox,usb";
816 status = "disabled";
817 hub {
818 compatible = "sandbox,usb-hub";
819 #address-cells = <1>;
820 #size-cells = <0>;
821 flash-stick {
822 reg = <0>;
823 compatible = "sandbox,usb-flash";
824 };
825 };
826 };
827
828 usb_1: usb@1 {
829 compatible = "sandbox,usb";
830 hub {
831 compatible = "usb-hub";
832 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +0200833 #address-cells = <1>;
834 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -0600835 hub-emul {
836 compatible = "sandbox,usb-hub";
837 #address-cells = <1>;
838 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700839 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600840 reg = <0>;
841 compatible = "sandbox,usb-flash";
842 sandbox,filepath = "testflash.bin";
843 };
844
Simon Glass4700fe52015-11-08 23:48:01 -0700845 flash-stick@1 {
846 reg = <1>;
847 compatible = "sandbox,usb-flash";
848 sandbox,filepath = "testflash1.bin";
849 };
850
851 flash-stick@2 {
852 reg = <2>;
853 compatible = "sandbox,usb-flash";
854 sandbox,filepath = "testflash2.bin";
855 };
856
Simon Glassc0ccc722015-11-08 23:48:08 -0700857 keyb@3 {
858 reg = <3>;
859 compatible = "sandbox,usb-keyb";
860 };
861
Simon Glass31680482015-03-25 12:23:05 -0600862 };
Michael Walle7c961322020-06-02 01:47:07 +0200863
864 usbstor@1 {
865 reg = <1>;
866 };
867 usbstor@3 {
868 reg = <3>;
869 };
Simon Glass31680482015-03-25 12:23:05 -0600870 };
871 };
872
873 usb_2: usb@2 {
874 compatible = "sandbox,usb";
875 status = "disabled";
876 };
877
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200878 spmi: spmi@0 {
879 compatible = "sandbox,spmi";
880 #address-cells = <0x1>;
881 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600882 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200883 pm8916@0 {
884 compatible = "qcom,spmi-pmic";
885 reg = <0x0 0x1>;
886 #address-cells = <0x1>;
887 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600888 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200889
890 spmi_gpios: gpios@c000 {
891 compatible = "qcom,pm8916-gpio";
892 reg = <0xc000 0x400>;
893 gpio-controller;
894 gpio-count = <4>;
895 #gpio-cells = <2>;
896 gpio-bank-name="spmi";
897 };
898 };
899 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700900
901 wdt0: wdt@0 {
902 compatible = "sandbox,wdt";
903 };
Rob Clarka471b672018-01-10 11:33:30 +0100904
Mario Six95922152018-08-09 14:51:19 +0200905 axi: axi@0 {
906 compatible = "sandbox,axi";
907 #address-cells = <0x1>;
908 #size-cells = <0x1>;
909 store@0 {
910 compatible = "sandbox,sandbox_store";
911 reg = <0x0 0x400>;
912 };
913 };
914
Rob Clarka471b672018-01-10 11:33:30 +0100915 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700916 #address-cells = <1>;
917 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -0700918 setting = "sunrise ohoka";
919 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -0700920 int-values = <0x1937 72993>;
Rob Clarka471b672018-01-10 11:33:30 +0100921 chosen-test {
922 compatible = "denx,u-boot-fdt-test";
923 reg = <9 1>;
924 };
925 };
Mario Six35616ef2018-03-12 14:53:33 +0100926
927 translation-test@8000 {
928 compatible = "simple-bus";
929 reg = <0x8000 0x4000>;
930
931 #address-cells = <0x2>;
932 #size-cells = <0x1>;
933
934 ranges = <0 0x0 0x8000 0x1000
935 1 0x100 0x9000 0x1000
936 2 0x200 0xA000 0x1000
937 3 0x300 0xB000 0x1000
938 >;
939
Fabien Dessenne22236e02019-05-31 15:11:30 +0200940 dma-ranges = <0 0x000 0x10000000 0x1000
941 1 0x100 0x20000000 0x1000
942 >;
943
Mario Six35616ef2018-03-12 14:53:33 +0100944 dev@0,0 {
945 compatible = "denx,u-boot-fdt-dummy";
946 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +0100947 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +0100948 };
949
950 dev@1,100 {
951 compatible = "denx,u-boot-fdt-dummy";
952 reg = <1 0x100 0x1000>;
953
954 };
955
956 dev@2,200 {
957 compatible = "denx,u-boot-fdt-dummy";
958 reg = <2 0x200 0x1000>;
959 };
960
961
962 noxlatebus@3,300 {
963 compatible = "simple-bus";
964 reg = <3 0x300 0x1000>;
965
966 #address-cells = <0x1>;
967 #size-cells = <0x0>;
968
969 dev@42 {
970 compatible = "denx,u-boot-fdt-dummy";
971 reg = <0x42>;
972 };
973 };
974 };
Mario Six02ad6fb2018-09-27 09:19:31 +0200975
976 osd {
977 compatible = "sandbox,sandbox_osd";
978 };
Tom Rinib93eea72018-09-30 18:16:51 -0400979
Mario Sixab664ff2018-07-31 11:44:13 +0200980 board {
981 compatible = "sandbox,board_sandbox";
982 };
Jens Wiklander86afaa62018-09-25 16:40:16 +0200983
984 sandbox_tee {
985 compatible = "sandbox,tee";
986 };
Bin Meng1bb290d2018-10-15 02:21:26 -0700987
988 sandbox_virtio1 {
989 compatible = "sandbox,virtio1";
990 };
991
992 sandbox_virtio2 {
993 compatible = "sandbox,virtio2";
994 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +0200995
996 pinctrl {
997 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +0100998
999 pinctrl-names = "default";
1000 pinctrl-0 = <&gpios>;
1001
1002 gpios: gpios {
1003 gpio0 {
1004 pins = "GPIO0";
1005 bias-pull-up;
1006 input-disable;
1007 };
1008 gpio1 {
1009 pins = "GPIO1";
1010 output-high;
1011 drive-open-drain;
1012 };
1013 gpio2 {
1014 pins = "GPIO2";
1015 bias-pull-down;
1016 input-enable;
1017 };
1018 gpio3 {
1019 pins = "GPIO3";
1020 bias-disable;
1021 };
1022 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001023 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001024
1025 hwspinlock@0 {
1026 compatible = "sandbox,hwspinlock";
1027 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001028
1029 dma: dma {
1030 compatible = "sandbox,dma";
1031 #dma-cells = <1>;
1032
1033 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1034 dma-names = "m2m", "tx0", "rx0";
1035 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001036
Alex Marginean0649be52019-07-12 10:13:53 +03001037 /*
1038 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1039 * end of the test. If parent mdio is removed first, clean-up of the
1040 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1041 * active at the end of the test. That it turn doesn't allow the mdio
1042 * class to be destroyed, triggering an error.
1043 */
1044 mdio-mux-test {
1045 compatible = "sandbox,mdio-mux";
1046 #address-cells = <1>;
1047 #size-cells = <0>;
1048 mdio-parent-bus = <&mdio>;
1049
1050 mdio-ch-test@0 {
1051 reg = <0>;
1052 };
1053 mdio-ch-test@1 {
1054 reg = <1>;
1055 };
1056 };
1057
1058 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001059 compatible = "sandbox,mdio";
1060 };
Sean Andersonb7860542020-06-24 06:41:12 -04001061
1062 pm-bus-test {
1063 compatible = "simple-pm-bus";
1064 clocks = <&clk_sandbox 4>;
1065 power-domains = <&pwrdom 1>;
1066 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001067
1068 resetc2: syscon-reset {
1069 compatible = "syscon-reset";
1070 #reset-cells = <1>;
1071 regmap = <&syscon0>;
1072 offset = <1>;
1073 mask = <0x27FFFFFF>;
1074 assert-high = <0>;
1075 };
1076
1077 syscon-reset-test {
1078 compatible = "sandbox,misc_sandbox";
1079 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1080 reset-names = "valid", "no_mask", "out_of_range";
1081 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001082};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001083
1084#include "sandbox_pmic.dtsi"