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git01.mediatek.com / filogic / uboot / 75f5606f5e29c83f969c887640ff9a28484e2390 / . / include / configs / meesc.h
blob: 55f64b559c75d340d2f910554d247f73e4527153 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]2/*
3 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +0100[diff] [blame]4 * Stelian Pop <stelian@popies.net>
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]5 * Lead Tech Design <www.leadtechdesign.com>
6 *
Daniel Gorsulowski2acb23b2015-11-02 07:59:49 +0100[diff] [blame]7 * (C) Copyright 2009-2015
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]8 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
9 * esd electronic system design gmbh <www.esd.eu>
10 *
11 * Configuation settings for the esd MEESC board.
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]12 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +0000[diff] [blame]17/*
18 * SoC must be defined first, before hardware.h is included.
19 * In this case SoC is defined in boards.cfg.
20 */
21#include <asm/hardware.h>
22
23/*
24 * Warning: changing CONFIG_SYS_TEXT_BASE requires
25 * adapting the initial boot program.
26 * Since the linker has to swallow that define, we must use a pure
27 * hex number here!
28 */
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +0000[diff] [blame]29
30/* ARM asynchronous clock */
31#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
Daniel Gorsulowski847726c2010-08-09 11:17:13 +0200[diff] [blame]32#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]33
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +0000[diff] [blame]34/* Misc CPU related */
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]35
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]36/*
37 * Hardware drivers
38 */
39
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]40/*
41 * BOOTP options
42 */
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +0000[diff] [blame]43#define CONFIG_BOOTP_BOOTFILESIZE
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]44
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +0000[diff] [blame]45/*
46 * SDRAM: 1 bank, min 32, max 128 MB
47 * Initialized before u-boot gets started.
48 */
Daniel Gorsulowski2acb23b2015-11-02 07:59:49 +0100[diff] [blame]49#define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */
50#define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */
51
Daniel Gorsulowski2acb23b2015-11-02 07:59:49 +0100[diff] [blame]52#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
53#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +0000[diff] [blame]54
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +0000[diff] [blame]55/*
56 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
57 * leaving the correct space for initial global data structure above
58 * that address while providing maximum stack area below.
59 */
60#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou.Yang@microchip.comcc2eca02017-07-21 17:06:40 +0800[diff] [blame]61 (ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]62
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]63/* NAND flash */
64#ifdef CONFIG_CMD_NAND
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +0000[diff] [blame]65# define CONFIG_SYS_MAX_NAND_DEVICE 1
Daniel Gorsulowski2acb23b2015-11-02 07:59:49 +0100[diff] [blame]66# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +0000[diff] [blame]67# define CONFIG_SYS_NAND_DBW_8
68# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
69# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmanna4c24d32013-11-29 12:13:45 +0100[diff] [blame]70# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
71# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]72#endif
73
74/* Ethernet */
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +0000[diff] [blame]75#define CONFIG_RMII
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]76#define CONFIG_NET_RETRY_COUNT 20
77#undef CONFIG_RESET_PHY_R
78
Daniel Gorsulowski54b531a2009-09-29 08:03:12 +0200[diff] [blame]79/* hw-controller addresses */
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +0000[diff] [blame]80#define CONFIG_ET1100_BASE 0x70000000
81
82#ifdef CONFIG_SYS_USE_DATAFLASH
Daniel Gorsulowski54b531a2009-09-29 08:03:12 +0200[diff] [blame]83
84/* bootstrap + u-boot + env in dataflash on CS0 */
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]85
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +0000[diff] [blame]86#elif CONFIG_SYS_USE_NANDFLASH
87
88/* bootstrap + u-boot + env + linux in nandflash */
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +0000[diff] [blame]89
90#endif
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]91
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +0000[diff] [blame]92#define CONFIG_SYS_CBSIZE 512
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]93
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +0200[diff] [blame]94#endif