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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese03915772014-10-22 12:13:18 +02002/*
Stefan Roese114bba62015-12-03 12:39:45 +01003 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
Stefan Roese03915772014-10-22 12:13:18 +02004 */
5
6#ifndef _CONFIG_DB_MV7846MP_GP_H
7#define _CONFIG_DB_MV7846MP_GP_H
8
9/*
10 * High Level Configuration Options (easy to change)
11 */
Stefan Roesef3679a32015-01-19 11:33:46 +010012#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
13
Stefan Roese3dbf35c2015-08-06 14:27:36 +020014/*
15 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
16 * for DDR ECC byte filling in the SPL before loading the main
17 * U-Boot into it.
18 */
Stefan Roese03915772014-10-22 12:13:18 +020019
Stefan Roese03915772014-10-22 12:13:18 +020020/* I2C */
Paul Kocialkowski2fae3e72015-04-10 23:09:51 +020021#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roese03915772014-10-22 12:13:18 +020022
Stefan Roese58613c72015-07-22 18:05:43 +020023/* USB/EHCI configuration */
Anton Schubert11b8ebf2015-07-23 15:02:09 +020024#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
Stefan Roese58613c72015-07-22 18:05:43 +020025
Stefan Roese03915772014-10-22 12:13:18 +020026/* Environment in SPI NOR flash */
Stefan Roese03915772014-10-22 12:13:18 +020027
Stefan Roese03915772014-10-22 12:13:18 +020028#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
Stefan Roese03915772014-10-22 12:13:18 +020029
Anton Schubert3ceae9e2015-07-15 14:50:05 +020030/* SATA support */
Stefan Roese114bba62015-12-03 12:39:45 +010031#define CONFIG_SYS_SATA_MAX_DEVICE 2
Stefan Roese114bba62015-12-03 12:39:45 +010032#define CONFIG_LBA48
Anton Schubert3ceae9e2015-07-15 14:50:05 +020033
Stefan Roese7d865292015-08-11 09:36:15 +020034/* PCIe support */
Stefan Roese83097cf2015-11-25 07:37:00 +010035#ifndef CONFIG_SPL_BUILD
Stefan Roese7d865292015-08-11 09:36:15 +020036#define CONFIG_PCI_SCAN_SHOW
Stefan Roese83097cf2015-11-25 07:37:00 +010037#endif
Stefan Roese7d865292015-08-11 09:36:15 +020038
Stefan Roese645949b2015-07-23 10:26:18 +020039/* NAND */
Stefan Roese645949b2015-07-23 10:26:18 +020040
Stefan Roese03915772014-10-22 12:13:18 +020041/*
42 * mv-common.h should be defined after CMD configs since it used them
43 * to enable certain macros
44 */
45#include "mv-common.h"
46
Stefan Roesef3679a32015-01-19 11:33:46 +010047/*
48 * Memory layout while starting into the bin_hdr via the
49 * BootROM:
50 *
51 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
52 * 0x4000.4030 bin_hdr start address
53 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
54 * 0x4007.fffc BootROM stack top
55 *
56 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
57 * L2 cache thus cannot be used.
58 */
59
60/* SPL */
61/* Defines for SPL */
Stefan Roesef3679a32015-01-19 11:33:46 +010062#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
63
64#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
65#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
66
Stefan Roese83097cf2015-11-25 07:37:00 +010067#ifdef CONFIG_SPL_BUILD
68#define CONFIG_SYS_MALLOC_SIMPLE
69#endif
Stefan Roesef3679a32015-01-19 11:33:46 +010070
71#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
72#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
73
Stefan Roesef3679a32015-01-19 11:33:46 +010074/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
Stefan Roesef3679a32015-01-19 11:33:46 +010075#define CONFIG_SPD_EEPROM 0x4e
Stefan Roeseff7ad172015-12-10 15:02:38 +010076#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
Stefan Roesef3679a32015-01-19 11:33:46 +010077
Stefan Roese03915772014-10-22 12:13:18 +020078#endif /* _CONFIG_DB_MV7846MP_GP_H */