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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
angelo@sysam.itf11cf752015-02-12 01:39:40 +01002/*
3 * Sysam AMCORE board configuration
4 *
Angelo Dureghello3b0d5702016-09-20 17:40:03 +02005 * (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it>
angelo@sysam.itf11cf752015-02-12 01:39:40 +01006 */
7
8#ifndef __AMCORE_CONFIG_H
9#define __AMCORE_CONFIG_H
10
Mario Six790d8442018-03-28 14:38:20 +020011#define CONFIG_HOSTNAME "AMCORE"
angelo@sysam.itf11cf752015-02-12 01:39:40 +010012
angelo@sysam.itf11cf752015-02-12 01:39:40 +010013#define CONFIG_MCFTMR
angelo@sysam.itf11cf752015-02-12 01:39:40 +010014#define CONFIG_SYS_UART_PORT 0
angelo@sysam.itf11cf752015-02-12 01:39:40 +010015
angelo@sysam.itf11cf752015-02-12 01:39:40 +010016#define CONFIG_BOOTCOMMAND "bootm ffc20000"
Angelo Dureghello3b0d5702016-09-20 17:40:03 +020017#define CONFIG_EXTRA_ENV_SETTINGS \
18 "upgrade_uboot=loady; " \
19 "protect off 0xffc00000 0xffc1ffff; " \
20 "erase 0xffc00000 0xffc1ffff; " \
21 "cp.b 0x20000 0xffc00000 ${filesize}\0" \
22 "upgrade_kernel=loady; " \
23 "erase 0xffc20000 0xffefffff; " \
24 "cp.b 0x20000 0xffc20000 ${filesize}\0" \
25 "upgrade_jffs2=loady; " \
26 "erase 0xfff00000 0xffffffff; " \
27 "cp.b 0x20000 0xfff00000 ${filesize}\0"
angelo@sysam.itf11cf752015-02-12 01:39:40 +010028
angelo@sysam.itf11cf752015-02-12 01:39:40 +010029#define CONFIG_SYS_CLK 45000000
30#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
31/* Register Base Addrs */
32#define CONFIG_SYS_MBAR 0x10000000
33/* Definitions for initial stack pointer and data area (in DPRAM) */
34#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
35/* size of internal SRAM */
36#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
37#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
38 GENERATED_GBL_DATA_SIZE)
39#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
40
41#define CONFIG_SYS_SDRAM_BASE 0x00000000
42#define CONFIG_SYS_SDRAM_SIZE 0x1000000
43#define CONFIG_SYS_FLASH_BASE 0xffc00000
44#define CONFIG_SYS_MAX_FLASH_BANKS 1
45#define CONFIG_SYS_MAX_FLASH_SECT 1024
46#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
47
angelo@sysam.itf11cf752015-02-12 01:39:40 +010048/* amcore design has flash data bytes wired swapped */
49#define CONFIG_SYS_WRITE_SWAPPED_DATA
50/* reserve 128-4KB */
51#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
52#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
angelo@sysam.itf11cf752015-02-12 01:39:40 +010053#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
54
angelo@sysam.it6312a952015-03-29 22:54:16 +020055#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -060056 . = DEFINED(env_offset) ? env_offset : .; \
57 env/embedded.o(.text*);
angelo@sysam.it6312a952015-03-29 22:54:16 +020058
angelo@sysam.itf11cf752015-02-12 01:39:40 +010059/* memory map space for linux boot data */
60#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
61
62/*
63 * Cache Configuration
64 *
65 * Special 8K version 3 core cache.
66 * This is a single unified instruction/data cache.
67 * sdram - single region - no masks
68 */
angelo@sysam.itf11cf752015-02-12 01:39:40 +010069
70#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
71 CONFIG_SYS_INIT_RAM_SIZE - 8)
72#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
73 CONFIG_SYS_INIT_RAM_SIZE - 4)
74#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
75#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
76 CF_ACR_EN)
77#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
78 CF_CACR_EC)
79
80/* CS0 - AMD Flash, address 0xffc00000 */
81#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
82/* 4MB, AA=0,V=1 C/I BIT for errata */
83#define CONFIG_SYS_CS0_MASK 0x003f0001
84/* WS=10, AA=1, PS=16bit (10) */
85#define CONFIG_SYS_CS0_CTRL 0x1980
86/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
87#define CONFIG_SYS_CS1_BASE 0x3000
88#define CONFIG_SYS_CS1_MASK 0x00070001
89#define CONFIG_SYS_CS1_CTRL 0x0100
90
91#endif /* __AMCORE_CONFIG_H */