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git01.mediatek.com / filogic / uboot / 75f5606f5e29c83f969c887640ff9a28484e2390 / . / arch / arm / dts / ast2600.dtsi
blob: 31905fd2085d6daeefafa691e38501d71ea41f9e [file] [log] [blame]
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/interrupt-controller/arm-gic.h>
3#include "skeleton.dtsi"
4
5/ {
6 model = "Aspeed BMC";
7 compatible = "aspeed,ast2600";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
11
12 aliases {
13 i2c0 = &i2c0;
14 i2c1 = &i2c1;
15 i2c2 = &i2c2;
16 i2c3 = &i2c3;
17 i2c4 = &i2c4;
18 i2c5 = &i2c5;
19 i2c6 = &i2c6;
20 i2c7 = &i2c7;
21 i2c8 = &i2c8;
22 i2c9 = &i2c9;
23 i2c10 = &i2c10;
24 i2c11 = &i2c11;
25 i2c12 = &i2c12;
26 i2c13 = &i2c13;
27 i2c14 = &i2c14;
28 i2c15 = &i2c15;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 serial6 = &uart7;
36 serial7 = &uart8;
37 serial8 = &uart9;
38 serial9 = &uart10;
39 serial10 = &uart11;
40 serial11 = &uart12;
41 serial12 = &uart13;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 enable-method = "aspeed,ast2600-smp";
48
49 cpu@0 {
50 compatible = "arm,cortex-a7";
51 device_type = "cpu";
52 reg = <0xf00>;
53 };
54
55 cpu@1 {
56 compatible = "arm,cortex-a7";
57 device_type = "cpu";
58 reg = <0xf01>;
59 };
60
61 };
62
63 timer {
64 compatible = "arm,armv7-timer";
65 interrupt-parent = <&gic>;
66 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
68 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
69 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
70 };
71
72 reserved-memory {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 gfx_memory: framebuffer {
78 size = <0x01000000>;
79 alignment = <0x01000000>;
80 compatible = "shared-dma-pool";
81 reusable;
82 };
83
84 video_memory: video {
85 size = <0x04000000>;
86 alignment = <0x01000000>;
87 compatible = "shared-dma-pool";
88 no-map;
89 };
90 };
91
92 ahb {
93 compatible = "simple-bus";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 device_type = "soc";
97 ranges;
98
99 gic: interrupt-controller@40461000 {
100 compatible = "arm,cortex-a7-gic";
101 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 interrupt-parent = <&gic>;
105 reg = <0x40461000 0x1000>,
106 <0x40462000 0x1000>,
107 <0x40464000 0x2000>,
108 <0x40466000 0x2000>;
109 };
110
111 ahbc: ahbc@1e600000 {
112 compatible = "aspeed,aspeed-ahbc";
113 reg = < 0x1e600000 0x100>;
114 };
115
116 fmc: flash-controller@1e620000 {
117 reg = < 0x1e620000 0xc4
118 0x20000000 0x10000000 >;
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "aspeed,ast2600-fmc";
122 status = "disabled";
123 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&scu ASPEED_CLK_AHB>;
125 num-cs = <3>;
126 flash@0 {
127 reg = < 0 >;
128 compatible = "jedec,spi-nor";
129 status = "disabled";
130 };
131 flash@1 {
132 reg = < 1 >;
133 compatible = "jedec,spi-nor";
134 status = "disabled";
135 };
136 flash@2 {
137 reg = < 2 >;
138 compatible = "jedec,spi-nor";
139 status = "disabled";
140 };
141 };
142
143 spi1: flash-controller@1e630000 {
144 reg = < 0x1e630000 0xc4
145 0x30000000 0x08000000 >;
146 #address-cells = <1>;
147 #size-cells = <0>;
148 compatible = "aspeed,ast2600-spi";
149 clocks = <&scu ASPEED_CLK_AHB>;
150 num-cs = <2>;
151 status = "disabled";
152 flash@0 {
153 reg = < 0 >;
154 compatible = "jedec,spi-nor";
155 status = "disabled";
156 };
157 flash@1 {
158 reg = < 1 >;
159 compatible = "jedec,spi-nor";
160 status = "disabled";
161 };
162 };
163
164 spi2: flash-controller@1e631000 {
165 reg = < 0x1e631000 0xc4
166 0x50000000 0x08000000 >;
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "aspeed,ast2600-spi";
170 clocks = <&scu ASPEED_CLK_AHB>;
171 num-cs = <3>;
172 status = "disabled";
173 flash@0 {
174 reg = < 0 >;
175 compatible = "jedec,spi-nor";
176 status = "disabled";
177 };
178 flash@1 {
179 reg = < 1 >;
180 compatible = "jedec,spi-nor";
181 status = "disabled";
182 };
183 flash@2 {
184 reg = < 2 >;
185 compatible = "jedec,spi-nor";
186 status = "disabled";
187 };
188 };
189
Joel Stanleyd18ef4f2021-10-27 14:17:28 +0800[diff] [blame]190 hace: hace@1e6d0000 {
191 compatible = "aspeed,ast2600-hace";
192 reg = <0x1e6d0000 0x200>;
193 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&scu ASPEED_CLK_GATE_YCLK>;
195 status = "disabled";
196 };
197
Chia-Wei Wang3435a3f2021-10-27 14:17:31 +0800[diff] [blame]198 acry: acry@1e6fa000 {
199 compatible = "aspeed,ast2600-acry";
200 reg = <0x1e6fa000 0x1000>,
201 <0x1e710000 0x10000>;
202 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&scu ASPEED_CLK_GATE_RSACLK>;
204 status = "disabled";
205 };
206
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]207 edac: sdram@1e6e0000 {
208 compatible = "aspeed,ast2600-sdram-edac";
209 reg = <0x1e6e0000 0x174>;
210 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
211 };
212
213 mdio: ethernet@1e650000 {
214 compatible = "aspeed,aspeed-mdio";
215 reg = <0x1e650000 0x40>;
216 resets = <&rst ASPEED_RESET_MII>;
217 status = "disabled";
218 };
219
220 mac0: ftgmac@1e660000 {
221 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
222 reg = <0x1e660000 0x180>, <0x1e650000 0x4>;
223 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>;
225 status = "disabled";
226 };
227
228 mac1: ftgmac@1e680000 {
229 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
230 reg = <0x1e680000 0x180>, <0x1e650008 0x4>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>;
235 status = "disabled";
236 };
237
238 mac2: ftgmac@1e670000 {
239 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
240 reg = <0x1e670000 0x180>, <0x1e650010 0x4>;
241 #address-cells = <1>;
242 #size-cells = <0>;
243 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>;
245 status = "disabled";
246 };
247
248 mac3: ftgmac@1e690000 {
249 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
250 reg = <0x1e690000 0x180>, <0x1e650018 0x4>;
251 #address-cells = <1>;
252 #size-cells = <0>;
253 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>;
255 status = "disabled";
256 };
257
258 ehci0: usb@1e6a1000 {
259 compatible = "aspeed,aspeed-ehci", "usb-ehci";
260 reg = <0x1e6a1000 0x100>;
261 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_usb2ah_default>;
265 status = "disabled";
266 };
267
268 ehci1: usb@1e6a3000 {
269 compatible = "aspeed,aspeed-ehci", "usb-ehci";
270 reg = <0x1e6a3000 0x100>;
271 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
272 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>;
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_usb2bh_default>;
275 status = "disabled";
276 };
277
278 apb {
279 compatible = "simple-bus";
280 #address-cells = <1>;
281 #size-cells = <1>;
282 ranges;
283
284 syscon: syscon@1e6e2000 {
285 compatible = "aspeed,g6-scu", "syscon", "simple-mfd";
286 reg = <0x1e6e2000 0x1000>;
287 #address-cells = <1>;
288 #size-cells = <1>;
289 #clock-cells = <1>;
290 #reset-cells = <1>;
291 ranges = <0 0x1e6e2000 0x1000>;
292
293 pinctrl: pinctrl {
294 compatible = "aspeed,g6-pinctrl";
295 aspeed,external-nodes = <&gfx &lhc>;
296
297 };
298
299 vga_scratch: scratch {
300 compatible = "aspeed,bmc-misc";
301 };
302
303 scu_ic0: interrupt-controller@0 {
304 #interrupt-cells = <1>;
305 compatible = "aspeed,ast2600-scu-ic";
306 reg = <0x560 0x10>;
307 interrupt-parent = <&gic>;
308 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
309 interrupt-controller;
310 };
311
312 scu_ic1: interrupt-controller@1 {
313 #interrupt-cells = <1>;
314 compatible = "aspeed,ast2600-scu-ic";
315 reg = <0x570 0x10>;
316 interrupt-parent = <&gic>;
317 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
318 interrupt-controller;
319 };
320
321 };
322
323 smp-memram@0 {
324 compatible = "aspeed,ast2600-smpmem", "syscon";
325 reg = <0x1e6e2180 0x40>;
326 };
327
328 gfx: display@1e6e6000 {
329 compatible = "aspeed,ast2500-gfx", "syscon";
330 reg = <0x1e6e6000 0x1000>;
331 reg-io-width = <4>;
332 };
333
334 pcie_bridge0: pcie@1e6ed000 {
335 compatible = "aspeed,ast2600-pcie";
336 #address-cells = <3>;
337 #size-cells = <2>;
338 reg = <0x1e6ed000 0x100>;
339 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000>,
340 <0x82000000 0x0 0x60000000 0x60000000 0x0 0x10000000>;
341 device_type = "pci";
342 bus-range = <0x00 0xff>;
343 resets = <&rst ASPEED_RESET_PCIE_DEV_O>;
344 cfg-handle = <&pcie_cfg0>;
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_pcie0rc_default>;
347
348 status = "disabled";
349 };
350
351 pcie_bridge1: pcie@1e6ed200 {
352 compatible = "aspeed,ast2600-pcie";
353 #address-cells = <3>;
354 #size-cells = <2>;
355 reg = <0x1e6ed200 0x100>;
356 ranges = <0x81000000 0x0 0x0 0x10000 0x00 0x10000>,
357 <0x82000000 0x0 0x70000000 0x70000000 0x0 0x10000000>;
358 device_type = "pci";
359 bus-range = <0x00 0xff>;
360 resets = <&rst ASPEED_RESET_PCIE_RC_O>;
361 cfg-handle = <&pcie_cfg1>;
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_pcie1rc_default>;
364
365 status = "disabled";
366 };
367
368 sdhci: sdhci@1e740000 {
369 #interrupt-cells = <1>;
370 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd";
371 reg = <0x1e740000 0x1000>;
372 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
373 interrupt-controller;
374 clocks = <&scu ASPEED_CLK_GATE_SDCLK>,
375 <&scu ASPEED_CLK_GATE_SDEXTCLK>;
376 clock-names = "ctrlclk", "extclk";
377 #address-cells = <1>;
378 #size-cells = <1>;
379 ranges = <0x0 0x1e740000 0x1000>;
380
381 sdhci_slot0: sdhci_slot0@100 {
382 compatible = "aspeed,sdhci-ast2600";
383 reg = <0x100 0x100>;
384 interrupts = <0>;
385 interrupt-parent = <&sdhci>;
386 sdhci,auto-cmd12;
387 clocks = <&scu ASPEED_CLK_SDIO>;
388 status = "disabled";
389 };
390
391 sdhci_slot1: sdhci_slot1@200 {
392 compatible = "aspeed,sdhci-ast2600";
393 reg = <0x200 0x100>;
394 interrupts = <1>;
395 interrupt-parent = <&sdhci>;
396 sdhci,auto-cmd12;
397 clocks = <&scu ASPEED_CLK_SDIO>;
398 status = "disabled";
399 };
400 };
401
402 emmc: emmc@1e750000 {
403 #interrupt-cells = <1>;
404 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd";
405 reg = <0x1e750000 0x1000>;
406 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
407 interrupt-controller;
408 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>,
409 <&scu ASPEED_CLK_GATE_EMMCEXTCLK>;
410 clock-names = "ctrlclk", "extclk";
411 #address-cells = <1>;
412 #size-cells = <1>;
413 ranges = <0x0 0x1e750000 0x1000>;
414
415 emmc_slot0: emmc_slot0@100 {
416 compatible = "aspeed,emmc-ast2600";
417 reg = <0x100 0x100>;
418 interrupts = <0>;
419 interrupt-parent = <&emmc>;
420 clocks = <&scu ASPEED_CLK_EMMC>;
421 status = "disabled";
422 };
423 };
424
425 h2x: h2x@1e770000 {
426 compatible = "aspeed,ast2600-h2x";
427 reg = <0x1e770000 0x100>;
428 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
429 resets = <&rst ASPEED_RESET_H2X>;
430 #address-cells = <1>;
431 #size-cells = <1>;
432 ranges = <0x0 0x1e770000 0x100>;
433
434 status = "disabled";
435
436 pcie_cfg0: cfg0@80 {
437 reg = <0x80 0x80>;
438 compatible = "aspeed,ast2600-pcie-cfg";
439 };
440
441 pcie_cfg1: cfg1@C0 {
442 compatible = "aspeed,ast2600-pcie-cfg";
443 reg = <0xC0 0x80>;
444 };
445 };
446
447 gpio0: gpio@1e780000 {
448 compatible = "aspeed,ast2600-gpio";
449 reg = <0x1e780000 0x1000>;
450 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
451 #gpio-cells = <2>;
452 gpio-controller;
453 interrupt-controller;
454 gpio-ranges = <&pinctrl 0 0 220>;
455 ngpios = <208>;
456 };
457
458 gpio1: gpio@1e780800 {
459 compatible = "aspeed,ast2600-gpio";
460 reg = <0x1e780800 0x800>;
461 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
462 #gpio-cells = <2>;
463 gpio-controller;
464 interrupt-controller;
465 gpio-ranges = <&pinctrl 0 0 208>;
466 ngpios = <36>;
467 };
468
469 uart1: serial@1e783000 {
470 compatible = "ns16550a";
471 reg = <0x1e783000 0x20>;
472 reg-shift = <2>;
473 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
475 clock-frequency = <1846154>;
476 no-loopback-test;
477 status = "disabled";
478 };
479
480 uart5: serial@1e784000 {
481 compatible = "ns16550a";
482 reg = <0x1e784000 0x1000>;
483 reg-shift = <2>;
484 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
486 clock-frequency = <1846154>;
487 no-loopback-test;
488 status = "disabled";
489 };
490
491 wdt1: watchdog@1e785000 {
492 compatible = "aspeed,ast2600-wdt";
493 reg = <0x1e785000 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]494 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]495 };
496
497 wdt2: watchdog@1e785040 {
498 compatible = "aspeed,ast2600-wdt";
499 reg = <0x1e785040 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]500 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]501 };
502
503 wdt3: watchdog@1e785080 {
504 compatible = "aspeed,ast2600-wdt";
505 reg = <0x1e785080 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]506 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]507 };
508
509 wdt4: watchdog@1e7850C0 {
510 compatible = "aspeed,ast2600-wdt";
511 reg = <0x1e7850C0 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]512 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]513 };
514
515 lpc: lpc@1e789000 {
516 compatible = "aspeed,ast2600-lpc", "simple-mfd", "syscon";
517 reg = <0x1e789000 0x1000>;
518
519 #address-cells = <1>;
520 #size-cells = <1>;
521 ranges = <0x0 0x1e789000 0x1000>;
522
523 kcs1: kcs1@0 {
524 compatible = "aspeed,ast2600-kcs-bmc";
525 reg = <0x0 0x80>;
526 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
527 kcs_chan = <1>;
528 kcs_addr = <0xCA0>;
529 status = "disabled";
530 };
531
532 kcs2: kcs2@0 {
533 compatible = "aspeed,ast2600-kcs-bmc";
534 reg = <0x0 0x80>;
535 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
536 kcs_chan = <2>;
537 kcs_addr = <0xCA8>;
538 status = "disabled";
539 };
540
541 kcs3: kcs3@0 {
542 compatible = "aspeed,ast2600-kcs-bmc";
543 reg = <0x0 0x80>;
544 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
545 kcs_chan = <3>;
546 kcs_addr = <0xCA2>;
547 };
548
549 kcs4: kcs4@0 {
550 compatible = "aspeed,ast2600-kcs-bmc";
551 reg = <0x0 0x120>;
552 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
553 kcs_chan = <4>;
554 kcs_addr = <0xCA4>;
555 status = "disabled";
556 };
557
558 lpc_ctrl: lpc-ctrl@80 {
559 compatible = "aspeed,ast2600-lpc-ctrl";
560 reg = <0x80 0x80>;
561 status = "disabled";
562 };
563
564 lpc_snoop: lpc-snoop@80 {
565 compatible = "aspeed,ast2600-lpc-snoop";
566 reg = <0x80 0x80>;
567 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
568 status = "disabled";
569 };
570
571 lhc: lhc@a0 {
572 compatible = "aspeed,ast2600-lhc";
573 reg = <0xa0 0x24 0xc8 0x8>;
574 };
575
576 lpc_reset: reset-controller@98 {
577 compatible = "aspeed,ast2600-lpc-reset";
578 reg = <0x98 0x4>;
579 #reset-cells = <1>;
580 status = "disabled";
581 };
582
583 ibt: ibt@140 {
584 compatible = "aspeed,ast2600-ibt-bmc";
585 reg = <0x140 0x18>;
586 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
587 status = "disabled";
588 };
589
590 sio_regs: regs {
591 compatible = "aspeed,bmc-misc";
592 };
593
594 mbox: mbox@200 {
595 compatible = "aspeed,ast2600-mbox";
596 reg = <0x200 0x5c>;
597 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
598 #mbox-cells = <1>;
599 status = "disabled";
600 };
601 };
602
603 uart2: serial@1e78d000 {
604 compatible = "ns16550a";
605 reg = <0x1e78d000 0x20>;
606 reg-shift = <2>;
607 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
609 clock-frequency = <1846154>;
610 no-loopback-test;
611 status = "disabled";
612 };
613
614 uart3: serial@1e78e000 {
615 compatible = "ns16550a";
616 reg = <0x1e78e000 0x20>;
617 reg-shift = <2>;
618 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
620 clock-frequency = <1846154>;
621 no-loopback-test;
622 status = "disabled";
623 };
624
625 uart4: serial@1e78f000 {
626 compatible = "ns16550a";
627 reg = <0x1e78f000 0x20>;
628 reg-shift = <2>;
629 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
631 clock-frequency = <1846154>;
632 no-loopback-test;
633 status = "disabled";
634 };
635
636 i2c: bus@1e78a000 {
637 compatible = "simple-bus";
638 #address-cells = <1>;
639 #size-cells = <1>;
640 ranges = <0 0x1e78a000 0x1000>;
641 };
642
643 fsim0: fsi@1e79b000 {
644 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
645 reg = <0x1e79b000 0x94>;
646 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&pinctrl_fsi1_default>;
649 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
650 status = "disabled";
651 };
652
653 fsim1: fsi@1e79b100 {
654 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
655 reg = <0x1e79b100 0x94>;
656 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
657 pinctrl-names = "default";
658 pinctrl-0 = <&pinctrl_fsi2_default>;
659 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
660 status = "disabled";
661 };
662
663 uart6: serial@1e790000 {
664 compatible = "ns16550a";
665 reg = <0x1e790000 0x20>;
666 reg-shift = <2>;
667 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>;
669 clock-frequency = <1846154>;
670 no-loopback-test;
671 status = "disabled";
672 };
673
674 uart7: serial@1e790100 {
675 compatible = "ns16550a";
676 reg = <0x1e790100 0x20>;
677 reg-shift = <2>;
678 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>;
680 clock-frequency = <1846154>;
681 no-loopback-test;
682 status = "disabled";
683 };
684
685 uart8: serial@1e790200 {
686 compatible = "ns16550a";
687 reg = <0x1e790200 0x20>;
688 reg-shift = <2>;
689 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>;
691 clock-frequency = <1846154>;
692 no-loopback-test;
693 status = "disabled";
694 };
695
696 uart9: serial@1e790300 {
697 compatible = "ns16550a";
698 reg = <0x1e790300 0x20>;
699 reg-shift = <2>;
700 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>;
702 clock-frequency = <1846154>;
703 no-loopback-test;
704 status = "disabled";
705 };
706
707 uart10: serial@1e790400 {
708 compatible = "ns16550a";
709 reg = <0x1e790400 0x20>;
710 reg-shift = <2>;
711 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>;
713 clock-frequency = <1846154>;
714 no-loopback-test;
715 status = "disabled";
716 };
717
718 uart11: serial@1e790500 {
719 compatible = "ns16550a";
720 reg = <0x1e790400 0x20>;
721 reg-shift = <2>;
722 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>;
724 clock-frequency = <1846154>;
725 no-loopback-test;
726 status = "disabled";
727 };
728
729 uart12: serial@1e790600 {
730 compatible = "ns16550a";
731 reg = <0x1e790600 0x20>;
732 reg-shift = <2>;
733 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>;
735 clock-frequency = <1846154>;
736 no-loopback-test;
737 status = "disabled";
738 };
739
740 uart13: serial@1e790700 {
741 compatible = "ns16550a";
742 reg = <0x1e790700 0x20>;
743 reg-shift = <2>;
744 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>;
746 clock-frequency = <1846154>;
747 no-loopback-test;
748 status = "disabled";
749 };
750
751 display_port: dp@1e6eb000 {
752 compatible = "aspeed,ast2600-displayport";
753 reg = <0x1e6eb000 0x200>;
754 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
755 resets = <&rst ASPEED_RESET_DP> ,<&rst ASPEED_RESET_DP_MCU>;
756 status = "disabled";
757 };
758
759 };
760
761 };
762
763};
764
765&i2c {
766 i2cglobal: i2cg@00 {
767 compatible = "aspeed,ast2600-i2c-global";
768 reg = <0x0 0x40>;
769 resets = <&rst ASPEED_RESET_I2C>;
770#if 0
771 new-mode;
772#endif
773 };
774
775 i2c0: i2c@80 {
776 #address-cells = <1>;
777 #size-cells = <0>;
778 #interrupt-cells = <1>;
779
780 reg = <0x80 0x80 0xC00 0x20>;
781 compatible = "aspeed,ast2600-i2c-bus";
782 bus-frequency = <100000>;
783 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&scu ASPEED_CLK_APB2>;
785 status = "disabled";
786 };
787
788 i2c1: i2c@100 {
789 #address-cells = <1>;
790 #size-cells = <0>;
791 #interrupt-cells = <1>;
792
793 reg = <0x100 0x80 0xC20 0x20>;
794 compatible = "aspeed,ast2600-i2c-bus";
795 bus-frequency = <100000>;
796 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
797 clocks = <&scu ASPEED_CLK_APB2>;
798 status = "disabled";
799 };
800
801 i2c2: i2c@180 {
802 #address-cells = <1>;
803 #size-cells = <0>;
804 #interrupt-cells = <1>;
805
806 reg = <0x180 0x80 0xC40 0x20>;
807 compatible = "aspeed,ast2600-i2c-bus";
808 bus-frequency = <100000>;
809 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&scu ASPEED_CLK_APB2>;
811 };
812
813 i2c3: i2c@200 {
814 #address-cells = <1>;
815 #size-cells = <0>;
816 #interrupt-cells = <1>;
817
818 reg = <0x200 0x40 0xC60 0x20>;
819 compatible = "aspeed,ast2600-i2c-bus";
820 bus-frequency = <100000>;
821 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&scu ASPEED_CLK_APB2>;
823 };
824
825 i2c4: i2c@280 {
826 #address-cells = <1>;
827 #size-cells = <0>;
828 #interrupt-cells = <1>;
829
830 reg = <0x280 0x80 0xC80 0x20>;
831 compatible = "aspeed,ast2600-i2c-bus";
832 bus-frequency = <100000>;
833 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&scu ASPEED_CLK_APB2>;
835 };
836
837 i2c5: i2c@300 {
838 #address-cells = <1>;
839 #size-cells = <0>;
840 #interrupt-cells = <1>;
841
842 reg = <0x300 0x40 0xCA0 0x20>;
843 compatible = "aspeed,ast2600-i2c-bus";
844 bus-frequency = <100000>;
845 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&scu ASPEED_CLK_APB2>;
847 };
848
849 i2c6: i2c@380 {
850 #address-cells = <1>;
851 #size-cells = <0>;
852 #interrupt-cells = <1>;
853
854 reg = <0x380 0x80 0xCC0 0x20>;
855 compatible = "aspeed,ast2600-i2c-bus";
856 bus-frequency = <100000>;
857 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&scu ASPEED_CLK_APB2>;
859 };
860
861 i2c7: i2c@400 {
862 #address-cells = <1>;
863 #size-cells = <0>;
864 #interrupt-cells = <1>;
865
866 reg = <0x400 0x80 0xCE0 0x20>;
867 compatible = "aspeed,ast2600-i2c-bus";
868 bus-frequency = <100000>;
869 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&scu ASPEED_CLK_APB2>;
871 };
872
873 i2c8: i2c@480 {
874 #address-cells = <1>;
875 #size-cells = <0>;
876 #interrupt-cells = <1>;
877
878 reg = <0x480 0x80 0xD00 0x20>;
879 compatible = "aspeed,ast2600-i2c-bus";
880 bus-frequency = <100000>;
881 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&scu ASPEED_CLK_APB2>;
883 };
884
885 i2c9: i2c@500 {
886 #address-cells = <1>;
887 #size-cells = <0>;
888 #interrupt-cells = <1>;
889
890 reg = <0x500 0x80 0xD20 0x20>;
891 compatible = "aspeed,ast2600-i2c-bus";
892 bus-frequency = <100000>;
893 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&scu ASPEED_CLK_APB2>;
895 status = "disabled";
896 };
897
898 i2c10: i2c@580 {
899 #address-cells = <1>;
900 #size-cells = <0>;
901 #interrupt-cells = <1>;
902
903 reg = <0x580 0x80 0xD40 0x20>;
904 compatible = "aspeed,ast2600-i2c-bus";
905 bus-frequency = <100000>;
906 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&scu ASPEED_CLK_APB2>;
908 status = "disabled";
909 };
910
911 i2c11: i2c@600 {
912 #address-cells = <1>;
913 #size-cells = <0>;
914 #interrupt-cells = <1>;
915
916 reg = <0x600 0x80 0xD60 0x20>;
917 compatible = "aspeed,ast2600-i2c-bus";
918 bus-frequency = <100000>;
919 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
920 clocks = <&scu ASPEED_CLK_APB2>;
921 status = "disabled";
922 };
923
924 i2c12: i2c@680 {
925 #address-cells = <1>;
926 #size-cells = <0>;
927 #interrupt-cells = <1>;
928
929 reg = <0x680 0x80 0xD80 0x20>;
930 compatible = "aspeed,ast2600-i2c-bus";
931 bus-frequency = <100000>;
932 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&scu ASPEED_CLK_APB2>;
934 status = "disabled";
935 };
936
937 i2c13: i2c@700 {
938 #address-cells = <1>;
939 #size-cells = <0>;
940 #interrupt-cells = <1>;
941
942 reg = <0x700 0x80 0xDA0 0x20>;
943 compatible = "aspeed,ast2600-i2c-bus";
944 bus-frequency = <100000>;
945 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&scu ASPEED_CLK_APB2>;
947 status = "disabled";
948 };
949
950 i2c14: i2c@780 {
951 #address-cells = <1>;
952 #size-cells = <0>;
953 #interrupt-cells = <1>;
954
955 reg = <0x780 0x80 0xDC0 0x20>;
956 compatible = "aspeed,ast2600-i2c-bus";
957 bus-frequency = <100000>;
958 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
959 clocks = <&scu ASPEED_CLK_APB2>;
960 status = "disabled";
961 };
962
963 i2c15: i2c@800 {
964 #address-cells = <1>;
965 #size-cells = <0>;
966 #interrupt-cells = <1>;
967
968 reg = <0x800 0x80 0xDE0 0x20>;
969 compatible = "aspeed,ast2600-i2c-bus";
970 bus-frequency = <100000>;
971 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
972 clocks = <&scu ASPEED_CLK_APB2>;
973 status = "disabled";
974 };
975
976};
977
978&pinctrl {
979 pinctrl_fmcquad_default: fmcquad_default {
980 function = "FMCQUAD";
981 groups = "FMCQUAD";
982 };
983
984 pinctrl_spi1_default: spi1_default {
985 function = "SPI1";
986 groups = "SPI1";
987 };
988
989 pinctrl_spi1abr_default: spi1abr_default {
990 function = "SPI1ABR";
991 groups = "SPI1ABR";
992 };
993
994 pinctrl_spi1cs1_default: spi1cs1_default {
995 function = "SPI1CS1";
996 groups = "SPI1CS1";
997 };
998
999 pinctrl_spi1wp_default: spi1wp_default {
1000 function = "SPI1WP";
1001 groups = "SPI1WP";
1002 };
1003
1004 pinctrl_spi1quad_default: spi1quad_default {
1005 function = "SPI1QUAD";
1006 groups = "SPI1QUAD";
1007 };
1008
1009 pinctrl_spi2_default: spi2_default {
1010 function = "SPI2";
1011 groups = "SPI2";
1012 };
1013
1014 pinctrl_spi2cs1_default: spi2cs1_default {
1015 function = "SPI2CS1";
1016 groups = "SPI2CS1";
1017 };
1018
1019 pinctrl_spi2cs2_default: spi2cs2_default {
1020 function = "SPI2CS2";
1021 groups = "SPI2CS2";
1022 };
1023
1024 pinctrl_spi2quad_default: spi2quad_default {
1025 function = "SPI2QUAD";
1026 groups = "SPI2QUAD";
1027 };
1028
1029 pinctrl_acpi_default: acpi_default {
1030 function = "ACPI";
1031 groups = "ACPI";
1032 };
1033
1034 pinctrl_adc0_default: adc0_default {
1035 function = "ADC0";
1036 groups = "ADC0";
1037 };
1038
1039 pinctrl_adc1_default: adc1_default {
1040 function = "ADC1";
1041 groups = "ADC1";
1042 };
1043
1044 pinctrl_adc10_default: adc10_default {
1045 function = "ADC10";
1046 groups = "ADC10";
1047 };
1048
1049 pinctrl_adc11_default: adc11_default {
1050 function = "ADC11";
1051 groups = "ADC11";
1052 };
1053
1054 pinctrl_adc12_default: adc12_default {
1055 function = "ADC12";
1056 groups = "ADC12";
1057 };
1058
1059 pinctrl_adc13_default: adc13_default {
1060 function = "ADC13";
1061 groups = "ADC13";
1062 };
1063
1064 pinctrl_adc14_default: adc14_default {
1065 function = "ADC14";
1066 groups = "ADC14";
1067 };
1068
1069 pinctrl_adc15_default: adc15_default {
1070 function = "ADC15";
1071 groups = "ADC15";
1072 };
1073
1074 pinctrl_adc2_default: adc2_default {
1075 function = "ADC2";
1076 groups = "ADC2";
1077 };
1078
1079 pinctrl_adc3_default: adc3_default {
1080 function = "ADC3";
1081 groups = "ADC3";
1082 };
1083
1084 pinctrl_adc4_default: adc4_default {
1085 function = "ADC4";
1086 groups = "ADC4";
1087 };
1088
1089 pinctrl_adc5_default: adc5_default {
1090 function = "ADC5";
1091 groups = "ADC5";
1092 };
1093
1094 pinctrl_adc6_default: adc6_default {
1095 function = "ADC6";
1096 groups = "ADC6";
1097 };
1098
1099 pinctrl_adc7_default: adc7_default {
1100 function = "ADC7";
1101 groups = "ADC7";
1102 };
1103
1104 pinctrl_adc8_default: adc8_default {
1105 function = "ADC8";
1106 groups = "ADC8";
1107 };
1108
1109 pinctrl_adc9_default: adc9_default {
1110 function = "ADC9";
1111 groups = "ADC9";
1112 };
1113
1114 pinctrl_bmcint_default: bmcint_default {
1115 function = "BMCINT";
1116 groups = "BMCINT";
1117 };
1118
1119 pinctrl_ddcclk_default: ddcclk_default {
1120 function = "DDCCLK";
1121 groups = "DDCCLK";
1122 };
1123
1124 pinctrl_ddcdat_default: ddcdat_default {
1125 function = "DDCDAT";
1126 groups = "DDCDAT";
1127 };
1128
1129 pinctrl_espi_default: espi_default {
1130 function = "ESPI";
1131 groups = "ESPI";
1132 };
1133
1134 pinctrl_fsi1_default: fsi1_default {
1135 function = "FSI1";
1136 groups = "FSI1";
1137 };
1138
1139 pinctrl_fsi2_default: fsi2_default {
1140 function = "FSI2";
1141 groups = "FSI2";
1142 };
1143
1144 pinctrl_fwspics1_default: fwspics1_default {
1145 function = "FWSPICS1";
1146 groups = "FWSPICS1";
1147 };
1148
1149 pinctrl_fwspics2_default: fwspics2_default {
1150 function = "FWSPICS2";
1151 groups = "FWSPICS2";
1152 };
1153
1154 pinctrl_gpid0_default: gpid0_default {
1155 function = "GPID0";
1156 groups = "GPID0";
1157 };
1158
1159 pinctrl_gpid2_default: gpid2_default {
1160 function = "GPID2";
1161 groups = "GPID2";
1162 };
1163
1164 pinctrl_gpid4_default: gpid4_default {
1165 function = "GPID4";
1166 groups = "GPID4";
1167 };
1168
1169 pinctrl_gpid6_default: gpid6_default {
1170 function = "GPID6";
1171 groups = "GPID6";
1172 };
1173
1174 pinctrl_gpie0_default: gpie0_default {
1175 function = "GPIE0";
1176 groups = "GPIE0";
1177 };
1178
1179 pinctrl_gpie2_default: gpie2_default {
1180 function = "GPIE2";
1181 groups = "GPIE2";
1182 };
1183
1184 pinctrl_gpie4_default: gpie4_default {
1185 function = "GPIE4";
1186 groups = "GPIE4";
1187 };
1188
1189 pinctrl_gpie6_default: gpie6_default {
1190 function = "GPIE6";
1191 groups = "GPIE6";
1192 };
1193
1194 pinctrl_i2c1_default: i2c1_default {
1195 function = "I2C1";
1196 groups = "I2C1";
1197 };
1198 pinctrl_i2c2_default: i2c2_default {
1199 function = "I2C2";
1200 groups = "I2C2";
1201 };
1202
1203 pinctrl_i2c3_default: i2c3_default {
1204 function = "I2C3";
1205 groups = "I2C3";
1206 };
1207
1208 pinctrl_i2c4_default: i2c4_default {
1209 function = "I2C4";
1210 groups = "I2C4";
1211 };
1212
1213 pinctrl_i2c5_default: i2c5_default {
1214 function = "I2C5";
1215 groups = "I2C5";
1216 };
1217
1218 pinctrl_i2c6_default: i2c6_default {
1219 function = "I2C6";
1220 groups = "I2C6";
1221 };
1222
1223 pinctrl_i2c7_default: i2c7_default {
1224 function = "I2C7";
1225 groups = "I2C7";
1226 };
1227
1228 pinctrl_i2c8_default: i2c8_default {
1229 function = "I2C8";
1230 groups = "I2C8";
1231 };
1232
1233 pinctrl_i2c9_default: i2c9_default {
1234 function = "I2C9";
1235 groups = "I2C9";
1236 };
1237
1238 pinctrl_i2c10_default: i2c10_default {
1239 function = "I2C10";
1240 groups = "I2C10";
1241 };
1242
1243 pinctrl_i2c11_default: i2c11_default {
1244 function = "I2C11";
1245 groups = "I2C11";
1246 };
1247
1248 pinctrl_i2c12_default: i2c12_default {
1249 function = "I2C12";
1250 groups = "I2C12";
1251 };
1252
1253 pinctrl_i2c13_default: i2c13_default {
1254 function = "I2C13";
1255 groups = "I2C13";
1256 };
1257
1258 pinctrl_i2c14_default: i2c14_default {
1259 function = "I2C14";
1260 groups = "I2C14";
1261 };
1262
1263 pinctrl_i2c15_default: i2c15_default {
1264 function = "I2C15";
1265 groups = "I2C15";
1266 };
1267
1268 pinctrl_i2c16_default: i2c16_default {
1269 function = "I2C16";
1270 groups = "I2C16";
1271 };
1272
1273 pinctrl_lad0_default: lad0_default {
1274 function = "LAD0";
1275 groups = "LAD0";
1276 };
1277
1278 pinctrl_lad1_default: lad1_default {
1279 function = "LAD1";
1280 groups = "LAD1";
1281 };
1282
1283 pinctrl_lad2_default: lad2_default {
1284 function = "LAD2";
1285 groups = "LAD2";
1286 };
1287
1288 pinctrl_lad3_default: lad3_default {
1289 function = "LAD3";
1290 groups = "LAD3";
1291 };
1292
1293 pinctrl_lclk_default: lclk_default {
1294 function = "LCLK";
1295 groups = "LCLK";
1296 };
1297
1298 pinctrl_lframe_default: lframe_default {
1299 function = "LFRAME";
1300 groups = "LFRAME";
1301 };
1302
1303 pinctrl_lpchc_default: lpchc_default {
1304 function = "LPCHC";
1305 groups = "LPCHC";
1306 };
1307
1308 pinctrl_lpcpd_default: lpcpd_default {
1309 function = "LPCPD";
1310 groups = "LPCPD";
1311 };
1312
1313 pinctrl_lpcplus_default: lpcplus_default {
1314 function = "LPCPLUS";
1315 groups = "LPCPLUS";
1316 };
1317
1318 pinctrl_lpcpme_default: lpcpme_default {
1319 function = "LPCPME";
1320 groups = "LPCPME";
1321 };
1322
1323 pinctrl_lpcrst_default: lpcrst_default {
1324 function = "LPCRST";
1325 groups = "LPCRST";
1326 };
1327
1328 pinctrl_lpcsmi_default: lpcsmi_default {
1329 function = "LPCSMI";
1330 groups = "LPCSMI";
1331 };
1332
1333 pinctrl_lsirq_default: lsirq_default {
1334 function = "LSIRQ";
1335 groups = "LSIRQ";
1336 };
1337
1338 pinctrl_mac1link_default: mac1link_default {
1339 function = "MAC1LINK";
1340 groups = "MAC1LINK";
1341 };
1342
1343 pinctrl_mac2link_default: mac2link_default {
1344 function = "MAC2LINK";
1345 groups = "MAC2LINK";
1346 };
1347
1348 pinctrl_mac3link_default: mac3link_default {
1349 function = "MAC3LINK";
1350 groups = "MAC3LINK";
1351 };
1352
1353 pinctrl_mac4link_default: mac4link_default {
1354 function = "MAC4LINK";
1355 groups = "MAC4LINK";
1356 };
1357
1358 pinctrl_mdio1_default: mdio1_default {
1359 function = "MDIO1";
1360 groups = "MDIO1";
1361 };
1362
1363 pinctrl_mdio2_default: mdio2_default {
1364 function = "MDIO2";
1365 groups = "MDIO2";
1366 };
1367
1368 pinctrl_mdio3_default: mdio3_default {
1369 function = "MDIO3";
1370 groups = "MDIO3";
1371 };
1372
1373 pinctrl_mdio4_default: mdio4_default {
1374 function = "MDIO4";
1375 groups = "MDIO4";
1376 };
1377
1378 pinctrl_rmii1_default: rmii1_default {
1379 function = "RMII1";
1380 groups = "RMII1";
1381 };
1382
1383 pinctrl_rmii2_default: rmii2_default {
1384 function = "RMII2";
1385 groups = "RMII2";
1386 };
1387
1388 pinctrl_rmii3_default: rmii3_default {
1389 function = "RMII3";
1390 groups = "RMII3";
1391 };
1392
1393 pinctrl_rmii4_default: rmii4_default {
1394 function = "RMII4";
1395 groups = "RMII4";
1396 };
1397
1398 pinctrl_rmii1rclk_default: rmii1rclk_default {
1399 function = "RMII1RCLK";
1400 groups = "RMII1RCLK";
1401 };
1402
1403 pinctrl_rmii2rclk_default: rmii2rclk_default {
1404 function = "RMII2RCLK";
1405 groups = "RMII2RCLK";
1406 };
1407
1408 pinctrl_rmii3rclk_default: rmii3rclk_default {
1409 function = "RMII3RCLK";
1410 groups = "RMII3RCLK";
1411 };
1412
1413 pinctrl_rmii4rclk_default: rmii4rclk_default {
1414 function = "RMII4RCLK";
1415 groups = "RMII4RCLK";
1416 };
1417
1418 pinctrl_ncts1_default: ncts1_default {
1419 function = "NCTS1";
1420 groups = "NCTS1";
1421 };
1422
1423 pinctrl_ncts2_default: ncts2_default {
1424 function = "NCTS2";
1425 groups = "NCTS2";
1426 };
1427
1428 pinctrl_ncts3_default: ncts3_default {
1429 function = "NCTS3";
1430 groups = "NCTS3";
1431 };
1432
1433 pinctrl_ncts4_default: ncts4_default {
1434 function = "NCTS4";
1435 groups = "NCTS4";
1436 };
1437
1438 pinctrl_ndcd1_default: ndcd1_default {
1439 function = "NDCD1";
1440 groups = "NDCD1";
1441 };
1442
1443 pinctrl_ndcd2_default: ndcd2_default {
1444 function = "NDCD2";
1445 groups = "NDCD2";
1446 };
1447
1448 pinctrl_ndcd3_default: ndcd3_default {
1449 function = "NDCD3";
1450 groups = "NDCD3";
1451 };
1452
1453 pinctrl_ndcd4_default: ndcd4_default {
1454 function = "NDCD4";
1455 groups = "NDCD4";
1456 };
1457
1458 pinctrl_ndsr1_default: ndsr1_default {
1459 function = "NDSR1";
1460 groups = "NDSR1";
1461 };
1462
1463 pinctrl_ndsr2_default: ndsr2_default {
1464 function = "NDSR2";
1465 groups = "NDSR2";
1466 };
1467
1468 pinctrl_ndsr3_default: ndsr3_default {
1469 function = "NDSR3";
1470 groups = "NDSR3";
1471 };
1472
1473 pinctrl_ndsr4_default: ndsr4_default {
1474 function = "NDSR4";
1475 groups = "NDSR4";
1476 };
1477
1478 pinctrl_ndtr1_default: ndtr1_default {
1479 function = "NDTR1";
1480 groups = "NDTR1";
1481 };
1482
1483 pinctrl_ndtr2_default: ndtr2_default {
1484 function = "NDTR2";
1485 groups = "NDTR2";
1486 };
1487
1488 pinctrl_ndtr3_default: ndtr3_default {
1489 function = "NDTR3";
1490 groups = "NDTR3";
1491 };
1492
1493 pinctrl_ndtr4_default: ndtr4_default {
1494 function = "NDTR4";
1495 groups = "NDTR4";
1496 };
1497
1498 pinctrl_nri1_default: nri1_default {
1499 function = "NRI1";
1500 groups = "NRI1";
1501 };
1502
1503 pinctrl_nri2_default: nri2_default {
1504 function = "NRI2";
1505 groups = "NRI2";
1506 };
1507
1508 pinctrl_nri3_default: nri3_default {
1509 function = "NRI3";
1510 groups = "NRI3";
1511 };
1512
1513 pinctrl_nri4_default: nri4_default {
1514 function = "NRI4";
1515 groups = "NRI4";
1516 };
1517
1518 pinctrl_nrts1_default: nrts1_default {
1519 function = "NRTS1";
1520 groups = "NRTS1";
1521 };
1522
1523 pinctrl_nrts2_default: nrts2_default {
1524 function = "NRTS2";
1525 groups = "NRTS2";
1526 };
1527
1528 pinctrl_nrts3_default: nrts3_default {
1529 function = "NRTS3";
1530 groups = "NRTS3";
1531 };
1532
1533 pinctrl_nrts4_default: nrts4_default {
1534 function = "NRTS4";
1535 groups = "NRTS4";
1536 };
1537
1538 pinctrl_oscclk_default: oscclk_default {
1539 function = "OSCCLK";
1540 groups = "OSCCLK";
1541 };
1542
1543 pinctrl_pewake_default: pewake_default {
1544 function = "PEWAKE";
1545 groups = "PEWAKE";
1546 };
1547
1548 pinctrl_pnor_default: pnor_default {
1549 function = "PNOR";
1550 groups = "PNOR";
1551 };
1552
1553 pinctrl_pwm0_default: pwm0_default {
1554 function = "PWM0";
1555 groups = "PWM0";
1556 };
1557
1558 pinctrl_pwm1_default: pwm1_default {
1559 function = "PWM1";
1560 groups = "PWM1";
1561 };
1562
1563 pinctrl_pwm2_default: pwm2_default {
1564 function = "PWM2";
1565 groups = "PWM2";
1566 };
1567
1568 pinctrl_pwm3_default: pwm3_default {
1569 function = "PWM3";
1570 groups = "PWM3";
1571 };
1572
1573 pinctrl_pwm4_default: pwm4_default {
1574 function = "PWM4";
1575 groups = "PWM4";
1576 };
1577
1578 pinctrl_pwm5_default: pwm5_default {
1579 function = "PWM5";
1580 groups = "PWM5";
1581 };
1582
1583 pinctrl_pwm6_default: pwm6_default {
1584 function = "PWM6";
1585 groups = "PWM6";
1586 };
1587
1588 pinctrl_pwm7_default: pwm7_default {
1589 function = "PWM7";
1590 groups = "PWM7";
1591 };
1592
1593 pinctrl_rgmii1_default: rgmii1_default {
1594 function = "RGMII1";
1595 groups = "RGMII1";
1596 };
1597
1598 pinctrl_rgmii2_default: rgmii2_default {
1599 function = "RGMII2";
1600 groups = "RGMII2";
1601 };
1602
1603 pinctrl_rgmii3_default: rgmii3_default {
1604 function = "RGMII3";
1605 groups = "RGMII3";
1606 };
1607
1608 pinctrl_rgmii4_default: rgmii4_default {
1609 function = "RGMII4";
1610 groups = "RGMII4";
1611 };
1612
1613 pinctrl_rmii1_default: rmii1_default {
1614 function = "RMII1";
1615 groups = "RMII1";
1616 };
1617
1618 pinctrl_rmii2_default: rmii2_default {
1619 function = "RMII2";
1620 groups = "RMII2";
1621 };
1622
1623 pinctrl_rxd1_default: rxd1_default {
1624 function = "RXD1";
1625 groups = "RXD1";
1626 };
1627
1628 pinctrl_rxd2_default: rxd2_default {
1629 function = "RXD2";
1630 groups = "RXD2";
1631 };
1632
1633 pinctrl_rxd3_default: rxd3_default {
1634 function = "RXD3";
1635 groups = "RXD3";
1636 };
1637
1638 pinctrl_rxd4_default: rxd4_default {
1639 function = "RXD4";
1640 groups = "RXD4";
1641 };
1642
1643 pinctrl_salt1_default: salt1_default {
1644 function = "SALT1";
1645 groups = "SALT1";
1646 };
1647
1648 pinctrl_salt10_default: salt10_default {
1649 function = "SALT10";
1650 groups = "SALT10";
1651 };
1652
1653 pinctrl_salt11_default: salt11_default {
1654 function = "SALT11";
1655 groups = "SALT11";
1656 };
1657
1658 pinctrl_salt12_default: salt12_default {
1659 function = "SALT12";
1660 groups = "SALT12";
1661 };
1662
1663 pinctrl_salt13_default: salt13_default {
1664 function = "SALT13";
1665 groups = "SALT13";
1666 };
1667
1668 pinctrl_salt14_default: salt14_default {
1669 function = "SALT14";
1670 groups = "SALT14";
1671 };
1672
1673 pinctrl_salt2_default: salt2_default {
1674 function = "SALT2";
1675 groups = "SALT2";
1676 };
1677
1678 pinctrl_salt3_default: salt3_default {
1679 function = "SALT3";
1680 groups = "SALT3";
1681 };
1682
1683 pinctrl_salt4_default: salt4_default {
1684 function = "SALT4";
1685 groups = "SALT4";
1686 };
1687
1688 pinctrl_salt5_default: salt5_default {
1689 function = "SALT5";
1690 groups = "SALT5";
1691 };
1692
1693 pinctrl_salt6_default: salt6_default {
1694 function = "SALT6";
1695 groups = "SALT6";
1696 };
1697
1698 pinctrl_salt7_default: salt7_default {
1699 function = "SALT7";
1700 groups = "SALT7";
1701 };
1702
1703 pinctrl_salt8_default: salt8_default {
1704 function = "SALT8";
1705 groups = "SALT8";
1706 };
1707
1708 pinctrl_salt9_default: salt9_default {
1709 function = "SALT9";
1710 groups = "SALT9";
1711 };
1712
1713 pinctrl_scl1_default: scl1_default {
1714 function = "SCL1";
1715 groups = "SCL1";
1716 };
1717
1718 pinctrl_scl2_default: scl2_default {
1719 function = "SCL2";
1720 groups = "SCL2";
1721 };
1722
1723 pinctrl_sd1_default: sd1_default {
1724 function = "SD1";
1725 groups = "SD1";
1726 };
1727
1728 pinctrl_sd2_default: sd2_default {
1729 function = "SD2";
1730 groups = "SD2";
1731 };
1732
1733 pinctrl_emmc_default: emmc_default {
1734 function = "EMMC";
1735 groups = "EMMC";
1736 };
1737
1738 pinctrl_emmcg8_default: emmcg8_default {
1739 function = "EMMCG8";
1740 groups = "EMMCG8";
1741 };
1742
1743 pinctrl_sda1_default: sda1_default {
1744 function = "SDA1";
1745 groups = "SDA1";
1746 };
1747
1748 pinctrl_sda2_default: sda2_default {
1749 function = "SDA2";
1750 groups = "SDA2";
1751 };
1752
1753 pinctrl_sgps1_default: sgps1_default {
1754 function = "SGPS1";
1755 groups = "SGPS1";
1756 };
1757
1758 pinctrl_sgps2_default: sgps2_default {
1759 function = "SGPS2";
1760 groups = "SGPS2";
1761 };
1762
1763 pinctrl_sioonctrl_default: sioonctrl_default {
1764 function = "SIOONCTRL";
1765 groups = "SIOONCTRL";
1766 };
1767
1768 pinctrl_siopbi_default: siopbi_default {
1769 function = "SIOPBI";
1770 groups = "SIOPBI";
1771 };
1772
1773 pinctrl_siopbo_default: siopbo_default {
1774 function = "SIOPBO";
1775 groups = "SIOPBO";
1776 };
1777
1778 pinctrl_siopwreq_default: siopwreq_default {
1779 function = "SIOPWREQ";
1780 groups = "SIOPWREQ";
1781 };
1782
1783 pinctrl_siopwrgd_default: siopwrgd_default {
1784 function = "SIOPWRGD";
1785 groups = "SIOPWRGD";
1786 };
1787
1788 pinctrl_sios3_default: sios3_default {
1789 function = "SIOS3";
1790 groups = "SIOS3";
1791 };
1792
1793 pinctrl_sios5_default: sios5_default {
1794 function = "SIOS5";
1795 groups = "SIOS5";
1796 };
1797
1798 pinctrl_siosci_default: siosci_default {
1799 function = "SIOSCI";
1800 groups = "SIOSCI";
1801 };
1802
1803 pinctrl_spi1_default: spi1_default {
1804 function = "SPI1";
1805 groups = "SPI1";
1806 };
1807
1808 pinctrl_spi1cs1_default: spi1cs1_default {
1809 function = "SPI1CS1";
1810 groups = "SPI1CS1";
1811 };
1812
1813 pinctrl_spi1debug_default: spi1debug_default {
1814 function = "SPI1DEBUG";
1815 groups = "SPI1DEBUG";
1816 };
1817
1818 pinctrl_spi1passthru_default: spi1passthru_default {
1819 function = "SPI1PASSTHRU";
1820 groups = "SPI1PASSTHRU";
1821 };
1822
1823 pinctrl_spi2ck_default: spi2ck_default {
1824 function = "SPI2CK";
1825 groups = "SPI2CK";
1826 };
1827
1828 pinctrl_spi2cs0_default: spi2cs0_default {
1829 function = "SPI2CS0";
1830 groups = "SPI2CS0";
1831 };
1832
1833 pinctrl_spi2cs1_default: spi2cs1_default {
1834 function = "SPI2CS1";
1835 groups = "SPI2CS1";
1836 };
1837
1838 pinctrl_spi2miso_default: spi2miso_default {
1839 function = "SPI2MISO";
1840 groups = "SPI2MISO";
1841 };
1842
1843 pinctrl_spi2mosi_default: spi2mosi_default {
1844 function = "SPI2MOSI";
1845 groups = "SPI2MOSI";
1846 };
1847
1848 pinctrl_timer3_default: timer3_default {
1849 function = "TIMER3";
1850 groups = "TIMER3";
1851 };
1852
1853 pinctrl_timer4_default: timer4_default {
1854 function = "TIMER4";
1855 groups = "TIMER4";
1856 };
1857
1858 pinctrl_timer5_default: timer5_default {
1859 function = "TIMER5";
1860 groups = "TIMER5";
1861 };
1862
1863 pinctrl_timer6_default: timer6_default {
1864 function = "TIMER6";
1865 groups = "TIMER6";
1866 };
1867
1868 pinctrl_timer7_default: timer7_default {
1869 function = "TIMER7";
1870 groups = "TIMER7";
1871 };
1872
1873 pinctrl_timer8_default: timer8_default {
1874 function = "TIMER8";
1875 groups = "TIMER8";
1876 };
1877
1878 pinctrl_txd1_default: txd1_default {
1879 function = "TXD1";
1880 groups = "TXD1";
1881 };
1882
1883 pinctrl_txd2_default: txd2_default {
1884 function = "TXD2";
1885 groups = "TXD2";
1886 };
1887
1888 pinctrl_txd3_default: txd3_default {
1889 function = "TXD3";
1890 groups = "TXD3";
1891 };
1892
1893 pinctrl_txd4_default: txd4_default {
1894 function = "TXD4";
1895 groups = "TXD4";
1896 };
1897
1898 pinctrl_uart6_default: uart6_default {
1899 function = "UART6";
1900 groups = "UART6";
1901 };
1902
1903 pinctrl_usbcki_default: usbcki_default {
1904 function = "USBCKI";
1905 groups = "USBCKI";
1906 };
1907
1908 pinctrl_usb2ah_default: usb2ah_default {
1909 function = "USB2AH";
1910 groups = "USB2AH";
1911 };
1912
1913 pinctrl_usb11bhid_default: usb11bhid_default {
1914 function = "USB11BHID";
1915 groups = "USB11BHID";
1916 };
1917
1918 pinctrl_usb2bh_default: usb2bh_default {
1919 function = "USB2BH";
1920 groups = "USB2BH";
1921 };
1922
1923 pinctrl_vgabiosrom_default: vgabiosrom_default {
1924 function = "VGABIOSROM";
1925 groups = "VGABIOSROM";
1926 };
1927
1928 pinctrl_vgahs_default: vgahs_default {
1929 function = "VGAHS";
1930 groups = "VGAHS";
1931 };
1932
1933 pinctrl_vgavs_default: vgavs_default {
1934 function = "VGAVS";
1935 groups = "VGAVS";
1936 };
1937
1938 pinctrl_vpi24_default: vpi24_default {
1939 function = "VPI24";
1940 groups = "VPI24";
1941 };
1942
1943 pinctrl_vpo_default: vpo_default {
1944 function = "VPO";
1945 groups = "VPO";
1946 };
1947
1948 pinctrl_wdtrst1_default: wdtrst1_default {
1949 function = "WDTRST1";
1950 groups = "WDTRST1";
1951 };
1952
1953 pinctrl_wdtrst2_default: wdtrst2_default {
1954 function = "WDTRST2";
1955 groups = "WDTRST2";
1956 };
1957
1958 pinctrl_pcie0rc_default: pcie0rc_default {
1959 function = "PCIE0RC";
1960 groups = "PCIE0RC";
1961 };
1962
1963 pinctrl_pcie1rc_default: pcie1rc_default {
1964 function = "PCIE1RC";
1965 groups = "PCIE1RC";
1966 };
1967};