| Michal Simek | f7b922a | 2021-05-10 13:14:02 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * MIO pin configuration defines for Xilinx ZynqMP |
| 4 | * |
| 5 | * Copyright (C) 2020 Xilinx, Inc. |
| 6 | */ |
| 7 | |
| 8 | #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H |
| 9 | #define _DT_BINDINGS_PINCTRL_ZYNQMP_H |
| 10 | |
| 11 | /* Bit value for different voltage levels */ |
| 12 | #define IO_STANDARD_LVCMOS33 0 |
| 13 | #define IO_STANDARD_LVCMOS18 1 |
| 14 | |
| 15 | /* Bit values for Slew Rates */ |
| 16 | #define SLEW_RATE_FAST 0 |
| 17 | #define SLEW_RATE_SLOW 1 |
| 18 | |
| 19 | #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ |