blob: ca2289225d37159a07fce23a5cf203748aee1795 [file] [log] [blame]
Aaron Williamsdcf16212022-04-07 09:11:42 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018-2022 Marvell International Ltd.
4 */
5
6#include <mach/cvmx-regs.h>
7#include <mach/octeon-model.h>
8#include <mach/cvmx-fuse.h>
9#include <mach/octeon-feature.h>
10#include <mach/cvmx-qlm.h>
11#include <mach/octeon_qlm.h>
12
13const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn63xx[] = {
14 { "prbs_err_cnt", 299, 252 }, // prbs_err_cnt[47..0]
15 { "prbs_lock", 251, 251 }, // prbs_lock
16 { "jtg_prbs_rst_n", 250, 250 }, // jtg_prbs_rst_n
17 { "jtg_run_prbs31", 249, 249 }, // jtg_run_prbs31
18 { "jtg_run_prbs7", 248, 248 }, // jtg_run_prbs7
19 { "Unused1", 247, 245 }, // 0
20 { "cfg_pwrup_set", 244, 244 }, // cfg_pwrup_set
21 { "cfg_pwrup_clr", 243, 243 }, // cfg_pwrup_clr
22 { "cfg_rst_n_set", 242, 242 }, // cfg_rst_n_set
23 { "cfg_rst_n_clr", 241, 241 }, // cfg_rst_n_clr
24 { "cfg_tx_idle_set", 240, 240 }, // cfg_tx_idle_set
25 { "cfg_tx_idle_clr", 239, 239 }, // cfg_tx_idle_clr
26 { "cfg_tx_byp", 238, 238 }, // cfg_tx_byp
27 { "cfg_tx_byp_inv", 237, 237 }, // cfg_tx_byp_inv
28 { "cfg_tx_byp_val", 236, 227 }, // cfg_tx_byp_val[9..0]
29 { "cfg_loopback", 226, 226 }, // cfg_loopback
30 { "shlpbck", 225, 224 }, // shlpbck[1..0]
31 { "sl_enable", 223, 223 }, // sl_enable
32 { "sl_posedge_sample", 222, 222 }, // sl_posedge_sample
33 { "trimen", 221, 220 }, // trimen[1..0]
34 { "serdes_tx_byp", 219, 219 }, // serdes_tx_byp
35 { "serdes_pll_byp", 218, 218 }, // serdes_pll_byp
36 { "lowf_byp", 217, 217 }, // lowf_byp
37 { "spdsel_byp", 216, 216 }, // spdsel_byp
38 { "div4_byp", 215, 215 }, // div4_byp
39 { "clkf_byp", 214, 208 }, // clkf_byp[6..0]
40 { "Unused2", 207, 206 }, // 0
41 { "biasdrv_hs_ls_byp", 205, 201 }, // biasdrv_hs_ls_byp[4..0]
42 { "tcoeff_hf_ls_byp", 200, 197 }, // tcoeff_hf_ls_byp[3..0]
43 { "biasdrv_hf_byp", 196, 192 }, // biasdrv_hf_byp[4..0]
44 { "tcoeff_hf_byp", 191, 188 }, // tcoeff_hf_byp[3..0]
45 { "Unused3", 187, 186 }, // 0
46 { "biasdrv_lf_ls_byp", 185, 181 }, // biasdrv_lf_ls_byp[4..0]
47 { "tcoeff_lf_ls_byp", 180, 177 }, // tcoeff_lf_ls_byp[3..0]
48 { "biasdrv_lf_byp", 176, 172 }, // biasdrv_lf_byp[4..0]
49 { "tcoeff_lf_byp", 171, 168 }, // tcoeff_lf_byp[3..0]
50 { "Unused4", 167, 167 }, // 0
51 { "interpbw", 166, 162 }, // interpbw[4..0]
52 { "pll_cpb", 161, 159 }, // pll_cpb[2..0]
53 { "pll_cps", 158, 156 }, // pll_cps[2..0]
54 { "pll_diffamp", 155, 152 }, // pll_diffamp[3..0]
55 { "Unused5", 151, 150 }, // 0
56 { "cfg_rx_idle_set", 149, 149 }, // cfg_rx_idle_set
57 { "cfg_rx_idle_clr", 148, 148 }, // cfg_rx_idle_clr
58 { "cfg_rx_idle_thr", 147, 144 }, // cfg_rx_idle_thr[3..0]
59 { "cfg_com_thr", 143, 140 }, // cfg_com_thr[3..0]
60 { "cfg_rx_offset", 139, 136 }, // cfg_rx_offset[3..0]
61 { "cfg_skp_max", 135, 132 }, // cfg_skp_max[3..0]
62 { "cfg_skp_min", 131, 128 }, // cfg_skp_min[3..0]
63 { "cfg_fast_pwrup", 127, 127 }, // cfg_fast_pwrup
64 { "Unused6", 126, 100 }, // 0
65 { "detected_n", 99, 99 }, // detected_n
66 { "detected_p", 98, 98 }, // detected_p
67 { "dbg_res_rx", 97, 94 }, // dbg_res_rx[3..0]
68 { "dbg_res_tx", 93, 90 }, // dbg_res_tx[3..0]
69 { "cfg_tx_pol_set", 89, 89 }, // cfg_tx_pol_set
70 { "cfg_tx_pol_clr", 88, 88 }, // cfg_tx_pol_clr
71 { "cfg_rx_pol_set", 87, 87 }, // cfg_rx_pol_set
72 { "cfg_rx_pol_clr", 86, 86 }, // cfg_rx_pol_clr
73 { "cfg_rxd_set", 85, 85 }, // cfg_rxd_set
74 { "cfg_rxd_clr", 84, 84 }, // cfg_rxd_clr
75 { "cfg_rxd_wait", 83, 80 }, // cfg_rxd_wait[3..0]
76 { "cfg_cdr_limit", 79, 79 }, // cfg_cdr_limit
77 { "cfg_cdr_rotate", 78, 78 }, // cfg_cdr_rotate
78 { "cfg_cdr_bw_ctl", 77, 76 }, // cfg_cdr_bw_ctl[1..0]
79 { "cfg_cdr_trunc", 75, 74 }, // cfg_cdr_trunc[1..0]
80 { "cfg_cdr_rqoffs", 73, 64 }, // cfg_cdr_rqoffs[9..0]
81 { "cfg_cdr_inc2", 63, 58 }, // cfg_cdr_inc2[5..0]
82 { "cfg_cdr_inc1", 57, 52 }, // cfg_cdr_inc1[5..0]
83 { "fusopt_voter_sync", 51, 51 }, // fusopt_voter_sync
84 { "rndt", 50, 50 }, // rndt
85 { "hcya", 49, 49 }, // hcya
86 { "hyst", 48, 48 }, // hyst
87 { "idle_dac", 47, 45 }, // idle_dac[2..0]
88 { "bg_ref_sel", 44, 44 }, // bg_ref_sel
89 { "ic50dac", 43, 39 }, // ic50dac[4..0]
90 { "ir50dac", 38, 34 }, // ir50dac[4..0]
91 { "tx_rout_comp_bypass", 33, 33 }, // tx_rout_comp_bypass
92 { "tx_rout_comp_value", 32, 29 }, // tx_rout_comp_value[3..0]
93 { "tx_res_offset", 28, 25 }, // tx_res_offset[3..0]
94 { "rx_rout_comp_bypass", 24, 24 }, // rx_rout_comp_bypass
95 { "rx_rout_comp_value", 23, 20 }, // rx_rout_comp_value[3..0]
96 { "rx_res_offset", 19, 16 }, // rx_res_offset[3..0]
97 { "rx_cap_gen2", 15, 12 }, // rx_cap_gen2[3..0]
98 { "rx_eq_gen2", 11, 8 }, // rx_eq_gen2[3..0]
99 { "rx_cap_gen1", 7, 4 }, // rx_cap_gen1[3..0]
100 { "rx_eq_gen1", 3, 0 }, // rx_eq_gen1[3..0]
101 { NULL, -1, -1 }
102};
103
104const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn66xx[] = {
105 { "prbs_err_cnt", 303, 256 }, // prbs_err_cnt[47..0]
106 { "prbs_lock", 255, 255 }, // prbs_lock
107 { "jtg_prbs_rx_rst_n", 254, 254 }, // jtg_prbs_rx_rst_n
108 { "jtg_prbs_tx_rst_n", 253, 253 }, // jtg_prbs_tx_rst_n
109 { "jtg_prbs_mode", 252, 251 }, // jtg_prbs_mode[252:251]
110 { "jtg_prbs_rst_n", 250, 250 }, // jtg_prbs_rst_n
111 { "jtg_run_prbs31", 249,
112 249 }, // jtg_run_prbs31 - Use jtg_prbs_mode instead
113 { "jtg_run_prbs7", 248,
114 248 }, // jtg_run_prbs7 - Use jtg_prbs_mode instead
115 { "Unused1", 247, 246 }, // 0
116 { "div5_byp", 245, 245 }, // div5_byp
117 { "cfg_pwrup_set", 244, 244 }, // cfg_pwrup_set
118 { "cfg_pwrup_clr", 243, 243 }, // cfg_pwrup_clr
119 { "cfg_rst_n_set", 242, 242 }, // cfg_rst_n_set
120 { "cfg_rst_n_clr", 241, 241 }, // cfg_rst_n_clr
121 { "cfg_tx_idle_set", 240, 240 }, // cfg_tx_idle_set
122 { "cfg_tx_idle_clr", 239, 239 }, // cfg_tx_idle_clr
123 { "cfg_tx_byp", 238, 238 }, // cfg_tx_byp
124 { "cfg_tx_byp_inv", 237, 237 }, // cfg_tx_byp_inv
125 { "cfg_tx_byp_val", 236, 227 }, // cfg_tx_byp_val[9..0]
126 { "cfg_loopback", 226, 226 }, // cfg_loopback
127 { "shlpbck", 225, 224 }, // shlpbck[1..0]
128 { "sl_enable", 223, 223 }, // sl_enable
129 { "sl_posedge_sample", 222, 222 }, // sl_posedge_sample
130 { "trimen", 221, 220 }, // trimen[1..0]
131 { "serdes_tx_byp", 219, 219 }, // serdes_tx_byp
132 { "serdes_pll_byp", 218, 218 }, // serdes_pll_byp
133 { "lowf_byp", 217, 217 }, // lowf_byp
134 { "spdsel_byp", 216, 216 }, // spdsel_byp
135 { "div4_byp", 215, 215 }, // div4_byp
136 { "clkf_byp", 214, 208 }, // clkf_byp[6..0]
137 { "biasdrv_hs_ls_byp", 207, 203 }, // biasdrv_hs_ls_byp[4..0]
138 { "tcoeff_hf_ls_byp", 202, 198 }, // tcoeff_hf_ls_byp[4..0]
139 { "biasdrv_hf_byp", 197, 193 }, // biasdrv_hf_byp[4..0]
140 { "tcoeff_hf_byp", 192, 188 }, // tcoeff_hf_byp[4..0]
141 { "biasdrv_lf_ls_byp", 187, 183 }, // biasdrv_lf_ls_byp[4..0]
142 { "tcoeff_lf_ls_byp", 182, 178 }, // tcoeff_lf_ls_byp[4..0]
143 { "biasdrv_lf_byp", 177, 173 }, // biasdrv_lf_byp[4..0]
144 { "tcoeff_lf_byp", 172, 168 }, // tcoeff_lf_byp[4..0]
145 { "Unused4", 167, 167 }, // 0
146 { "interpbw", 166, 162 }, // interpbw[4..0]
147 { "pll_cpb", 161, 159 }, // pll_cpb[2..0]
148 { "pll_cps", 158, 156 }, // pll_cps[2..0]
149 { "pll_diffamp", 155, 152 }, // pll_diffamp[3..0]
150 { "cfg_err_thr", 151, 150 }, // cfg_err_thr
151 { "cfg_rx_idle_set", 149, 149 }, // cfg_rx_idle_set
152 { "cfg_rx_idle_clr", 148, 148 }, // cfg_rx_idle_clr
153 { "cfg_rx_idle_thr", 147, 144 }, // cfg_rx_idle_thr[3..0]
154 { "cfg_com_thr", 143, 140 }, // cfg_com_thr[3..0]
155 { "cfg_rx_offset", 139, 136 }, // cfg_rx_offset[3..0]
156 { "cfg_skp_max", 135, 132 }, // cfg_skp_max[3..0]
157 { "cfg_skp_min", 131, 128 }, // cfg_skp_min[3..0]
158 { "cfg_fast_pwrup", 127, 127 }, // cfg_fast_pwrup
159 { "Unused6", 126, 101 }, // 0
160 { "cfg_indep_dis", 100, 100 }, // cfg_indep_dis
161 { "detected_n", 99, 99 }, // detected_n
162 { "detected_p", 98, 98 }, // detected_p
163 { "dbg_res_rx", 97, 94 }, // dbg_res_rx[3..0]
164 { "dbg_res_tx", 93, 90 }, // dbg_res_tx[3..0]
165 { "cfg_tx_pol_set", 89, 89 }, // cfg_tx_pol_set
166 { "cfg_tx_pol_clr", 88, 88 }, // cfg_tx_pol_clr
167 { "cfg_rx_pol_set", 87, 87 }, // cfg_rx_pol_set
168 { "cfg_rx_pol_clr", 86, 86 }, // cfg_rx_pol_clr
169 { "cfg_rxd_set", 85, 85 }, // cfg_rxd_set
170 { "cfg_rxd_clr", 84, 84 }, // cfg_rxd_clr
171 { "cfg_rxd_wait", 83, 80 }, // cfg_rxd_wait[3..0]
172 { "cfg_cdr_limit", 79, 79 }, // cfg_cdr_limit
173 { "cfg_cdr_rotate", 78, 78 }, // cfg_cdr_rotate
174 { "cfg_cdr_bw_ctl", 77, 76 }, // cfg_cdr_bw_ctl[1..0]
175 { "cfg_cdr_trunc", 75, 74 }, // cfg_cdr_trunc[1..0]
176 { "cfg_cdr_rqoffs", 73, 64 }, // cfg_cdr_rqoffs[9..0]
177 { "cfg_cdr_inc2", 63, 58 }, // cfg_cdr_inc2[5..0]
178 { "cfg_cdr_inc1", 57, 52 }, // cfg_cdr_inc1[5..0]
179 { "fusopt_voter_sync", 51, 51 }, // fusopt_voter_sync
180 { "rndt", 50, 50 }, // rndt
181 { "hcya", 49, 49 }, // hcya
182 { "hyst", 48, 48 }, // hyst
183 { "idle_dac", 47, 45 }, // idle_dac[2..0]
184 { "bg_ref_sel", 44, 44 }, // bg_ref_sel
185 { "ic50dac", 43, 39 }, // ic50dac[4..0]
186 { "ir50dac", 38, 34 }, // ir50dac[4..0]
187 { "tx_rout_comp_bypass", 33, 33 }, // tx_rout_comp_bypass
188 { "tx_rout_comp_value", 32, 29 }, // tx_rout_comp_value[3..0]
189 { "tx_res_offset", 28, 25 }, // tx_res_offset[3..0]
190 { "rx_rout_comp_bypass", 24, 24 }, // rx_rout_comp_bypass
191 { "rx_rout_comp_value", 23, 20 }, // rx_rout_comp_value[3..0]
192 { "rx_res_offset", 19, 16 }, // rx_res_offset[3..0]
193 { "rx_cap_gen2", 15, 12 }, // rx_cap_gen2[3..0]
194 { "rx_eq_gen2", 11, 8 }, // rx_eq_gen2[3..0]
195 { "rx_cap_gen1", 7, 4 }, // rx_cap_gen1[3..0]
196 { "rx_eq_gen1", 3, 0 }, // rx_eq_gen1[3..0]
197 { NULL, -1, -1 }
198};
199
200const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn68xx[] = {
201 { "prbs_err_cnt", 303, 256 }, // prbs_err_cnt[47..0]
202 { "prbs_lock", 255, 255 }, // prbs_lock
203 { "jtg_prbs_rx_rst_n", 254, 254 }, // jtg_prbs_rx_rst_n
204 { "jtg_prbs_tx_rst_n", 253, 253 }, // jtg_prbs_tx_rst_n
205 { "jtg_prbs_mode", 252, 251 }, // jtg_prbs_mode[252:251]
206 { "jtg_prbs_rst_n", 250, 250 }, // jtg_prbs_rst_n
207 { "jtg_run_prbs31", 249,
208 249 }, // jtg_run_prbs31 - Use jtg_prbs_mode instead
209 { "jtg_run_prbs7", 248,
210 248 }, // jtg_run_prbs7 - Use jtg_prbs_mode instead
211 { "Unused1", 247, 245 }, // 0
212 { "cfg_pwrup_set", 244, 244 }, // cfg_pwrup_set
213 { "cfg_pwrup_clr", 243, 243 }, // cfg_pwrup_clr
214 { "cfg_rst_n_set", 242, 242 }, // cfg_rst_n_set
215 { "cfg_rst_n_clr", 241, 241 }, // cfg_rst_n_clr
216 { "cfg_tx_idle_set", 240, 240 }, // cfg_tx_idle_set
217 { "cfg_tx_idle_clr", 239, 239 }, // cfg_tx_idle_clr
218 { "cfg_tx_byp", 238, 238 }, // cfg_tx_byp
219 { "cfg_tx_byp_inv", 237, 237 }, // cfg_tx_byp_inv
220 { "cfg_tx_byp_val", 236, 227 }, // cfg_tx_byp_val[9..0]
221 { "cfg_loopback", 226, 226 }, // cfg_loopback
222 { "shlpbck", 225, 224 }, // shlpbck[1..0]
223 { "sl_enable", 223, 223 }, // sl_enable
224 { "sl_posedge_sample", 222, 222 }, // sl_posedge_sample
225 { "trimen", 221, 220 }, // trimen[1..0]
226 { "serdes_tx_byp", 219, 219 }, // serdes_tx_byp
227 { "serdes_pll_byp", 218, 218 }, // serdes_pll_byp
228 { "lowf_byp", 217, 217 }, // lowf_byp
229 { "spdsel_byp", 216, 216 }, // spdsel_byp
230 { "div4_byp", 215, 215 }, // div4_byp
231 { "clkf_byp", 214, 208 }, // clkf_byp[6..0]
232 { "biasdrv_hs_ls_byp", 207, 203 }, // biasdrv_hs_ls_byp[4..0]
233 { "tcoeff_hf_ls_byp", 202, 198 }, // tcoeff_hf_ls_byp[4..0]
234 { "biasdrv_hf_byp", 197, 193 }, // biasdrv_hf_byp[4..0]
235 { "tcoeff_hf_byp", 192, 188 }, // tcoeff_hf_byp[4..0]
236 { "biasdrv_lf_ls_byp", 187, 183 }, // biasdrv_lf_ls_byp[4..0]
237 { "tcoeff_lf_ls_byp", 182, 178 }, // tcoeff_lf_ls_byp[4..0]
238 { "biasdrv_lf_byp", 177, 173 }, // biasdrv_lf_byp[4..0]
239 { "tcoeff_lf_byp", 172, 168 }, // tcoeff_lf_byp[4..0]
240 { "Unused4", 167, 167 }, // 0
241 { "interpbw", 166, 162 }, // interpbw[4..0]
242 { "pll_cpb", 161, 159 }, // pll_cpb[2..0]
243 { "pll_cps", 158, 156 }, // pll_cps[2..0]
244 { "pll_diffamp", 155, 152 }, // pll_diffamp[3..0]
245 { "cfg_err_thr", 151, 150 }, // cfg_err_thr
246 { "cfg_rx_idle_set", 149, 149 }, // cfg_rx_idle_set
247 { "cfg_rx_idle_clr", 148, 148 }, // cfg_rx_idle_clr
248 { "cfg_rx_idle_thr", 147, 144 }, // cfg_rx_idle_thr[3..0]
249 { "cfg_com_thr", 143, 140 }, // cfg_com_thr[3..0]
250 { "cfg_rx_offset", 139, 136 }, // cfg_rx_offset[3..0]
251 { "cfg_skp_max", 135, 132 }, // cfg_skp_max[3..0]
252 { "cfg_skp_min", 131, 128 }, // cfg_skp_min[3..0]
253 { "cfg_fast_pwrup", 127, 127 }, // cfg_fast_pwrup
254 { "Unused6", 126, 100 }, // 0
255 { "detected_n", 99, 99 }, // detected_n
256 { "detected_p", 98, 98 }, // detected_p
257 { "dbg_res_rx", 97, 94 }, // dbg_res_rx[3..0]
258 { "dbg_res_tx", 93, 90 }, // dbg_res_tx[3..0]
259 { "cfg_tx_pol_set", 89, 89 }, // cfg_tx_pol_set
260 { "cfg_tx_pol_clr", 88, 88 }, // cfg_tx_pol_clr
261 { "cfg_rx_pol_set", 87, 87 }, // cfg_rx_pol_set
262 { "cfg_rx_pol_clr", 86, 86 }, // cfg_rx_pol_clr
263 { "cfg_rxd_set", 85, 85 }, // cfg_rxd_set
264 { "cfg_rxd_clr", 84, 84 }, // cfg_rxd_clr
265 { "cfg_rxd_wait", 83, 80 }, // cfg_rxd_wait[3..0]
266 { "cfg_cdr_limit", 79, 79 }, // cfg_cdr_limit
267 { "cfg_cdr_rotate", 78, 78 }, // cfg_cdr_rotate
268 { "cfg_cdr_bw_ctl", 77, 76 }, // cfg_cdr_bw_ctl[1..0]
269 { "cfg_cdr_trunc", 75, 74 }, // cfg_cdr_trunc[1..0]
270 { "cfg_cdr_rqoffs", 73, 64 }, // cfg_cdr_rqoffs[9..0]
271 { "cfg_cdr_inc2", 63, 58 }, // cfg_cdr_inc2[5..0]
272 { "cfg_cdr_inc1", 57, 52 }, // cfg_cdr_inc1[5..0]
273 { "fusopt_voter_sync", 51, 51 }, // fusopt_voter_sync
274 { "rndt", 50, 50 }, // rndt
275 { "hcya", 49, 49 }, // hcya
276 { "hyst", 48, 48 }, // hyst
277 { "idle_dac", 47, 45 }, // idle_dac[2..0]
278 { "bg_ref_sel", 44, 44 }, // bg_ref_sel
279 { "ic50dac", 43, 39 }, // ic50dac[4..0]
280 { "ir50dac", 38, 34 }, // ir50dac[4..0]
281 { "tx_rout_comp_bypass", 33, 33 }, // tx_rout_comp_bypass
282 { "tx_rout_comp_value", 32, 29 }, // tx_rout_comp_value[3..0]
283 { "tx_res_offset", 28, 25 }, // tx_res_offset[3..0]
284 { "rx_rout_comp_bypass", 24, 24 }, // rx_rout_comp_bypass
285 { "rx_rout_comp_value", 23, 20 }, // rx_rout_comp_value[3..0]
286 { "rx_res_offset", 19, 16 }, // rx_res_offset[3..0]
287 { "rx_cap_gen2", 15, 12 }, // rx_cap_gen2[3..0]
288 { "rx_eq_gen2", 11, 8 }, // rx_eq_gen2[3..0]
289 { "rx_cap_gen1", 7, 4 }, // rx_cap_gen1[3..0]
290 { "rx_eq_gen1", 3, 0 }, // rx_eq_gen1[3..0]
291 { NULL, -1, -1 }
292};