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git01.mediatek.com / filogic / uboot / 756bf0ef4bab765e29cd3cb70bac8b1aaa014378 / . / arch / arm / dts / rv1126-u-boot.dtsi
blob: 4485980135783c70f377103e70fefb6a691cedb4 [file] [log] [blame]
Jagan Teki688b0fe2022-12-14 23:21:10 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
4 */
5
6#include "rockchip-u-boot.dtsi"
7
8/ {
9 chosen {
10 u-boot,spl-boot-order = \
11 "same-as-spl", &emmc, &sdmmc;
12 };
13
14 dmc {
15 compatible = "rockchip,rv1126-dmc";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]16 bootph-all;
Jagan Teki688b0fe2022-12-14 23:21:10 +0530[diff] [blame]17 };
Tim Lunncbfee492023-10-31 13:07:15 +1100[diff] [blame]18
19 otp: otp@ff5c0000 {
20 compatible = "rockchip,rv1126-otp";
21 reg = <0xff5c0000 0x1000>;
22 #address-cells = <1>;
23 #size-cells = <1>;
24 status = "okay";
25
26 cpu_id: id@7 {
27 reg = <0x07 0x10>;
28 };
29 };
Jagan Teki688b0fe2022-12-14 23:21:10 +0530[diff] [blame]30};
31
32&gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Jagan Teki688b0fe2022-12-14 23:21:10 +0530[diff] [blame]34};
35
36&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Jagan Teki688b0fe2022-12-14 23:21:10 +0530[diff] [blame]38};
39
40&grf {
Tim Lunn063bb9c2023-10-31 00:12:41 +1100[diff] [blame]41 bootph-all;
Jagan Teki688b0fe2022-12-14 23:21:10 +0530[diff] [blame]42};
43
44&pmu {
Tim Lunn063bb9c2023-10-31 00:12:41 +1100[diff] [blame]45 bootph-all;
Jagan Teki688b0fe2022-12-14 23:21:10 +0530[diff] [blame]46};
47
48&pmugrf {
Tim Lunn063bb9c2023-10-31 00:12:41 +1100[diff] [blame]49 bootph-all;
Jagan Teki688b0fe2022-12-14 23:21:10 +0530[diff] [blame]50};
51
52&xin24m {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Jagan Teki688b0fe2022-12-14 23:21:10 +0530[diff] [blame]54};
55
56&cru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Jagan Teki688b0fe2022-12-14 23:21:10 +0530[diff] [blame]58};
59
60&pmucru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Jagan Teki688b0fe2022-12-14 23:21:10 +0530[diff] [blame]62};
63
64&sdmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Jagan Teki688b0fe2022-12-14 23:21:10 +0530[diff] [blame]66};
67
68&emmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Jagan Teki688b0fe2022-12-14 23:21:10 +0530[diff] [blame]70};
71
72&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Jagan Teki688b0fe2022-12-14 23:21:10 +0530[diff] [blame]74};