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git01.mediatek.com / filogic / uboot / 756bf0ef4bab765e29cd3cb70bac8b1aaa014378 / . / arch / arm / dts / rk3568-lubancat-2.dts
blob: a8a4cc190eb32e2cf18d9ab7f8549a96c12a6465 [file] [log] [blame]
Andy Yanb352c842023-08-05 20:00:11 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3/*
4 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
5 * Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
6 */
7
8/dts-v1/;
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/pinctrl/rockchip.h>
12#include <dt-bindings/soc/rockchip,vop2.h>
13#include "rk3568.dtsi"
14
15/ {
16 model = "EmbedFire LubanCat 2";
17 compatible = "embedfire,lubancat-2", "rockchip,rk3568";
18
19 aliases {
20 ethernet0 = &gmac0;
21 ethernet1 = &gmac1;
22 mmc0 = &sdmmc0;
23 mmc1 = &sdhci;
24 };
25
26 chosen: chosen {
27 stdout-path = "serial2:1500000n8";
28 };
29
30 leds {
31 compatible = "gpio-leds";
32
33 user_led: user-led {
34 label = "user_led";
35 linux,default-trigger = "heartbeat";
36 default-state = "on";
37 gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
38 pinctrl-names = "default";
39 pinctrl-0 = <&user_led_pin>;
40 };
41 };
42
43 hdmi-con {
44 compatible = "hdmi-connector";
45 type = "a";
46
47 port {
48 hdmi_con_in: endpoint {
49 remote-endpoint = <&hdmi_out_con>;
50 };
51 };
52 };
53
54 dc_5v: dc-5v-regulator {
55 compatible = "regulator-fixed";
56 regulator-name = "dc_5v";
57 regulator-always-on;
58 regulator-boot-on;
59 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <5000000>;
61 };
62
63 vcc3v3_sys: vcc3v3-sys-regulator {
64 compatible = "regulator-fixed";
65 regulator-name = "vcc3v3_sys";
66 regulator-always-on;
67 regulator-boot-on;
68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <3300000>;
70 vin-supply = <&vcc5v0_sys>;
71 };
72
73 vcc5v0_sys: vcc5v0-sys-regulator {
74 compatible = "regulator-fixed";
75 regulator-name = "vcc5v0_sys";
76 regulator-always-on;
77 regulator-boot-on;
78 regulator-min-microvolt = <5000000>;
79 regulator-max-microvolt = <5000000>;
80 vin-supply = <&dc_5v>;
81 };
82
83 vcc3v3_m2_pcie: vcc3v3-m2-pcie-regulator {
84 compatible = "regulator-fixed";
85 regulator-name = "m2_pcie_3v3";
86 enable-active-high;
87 regulator-min-microvolt = <3300000>;
88 regulator-max-microvolt = <3300000>;
89 gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
90 pinctrl-0 = <&vcc3v3_m2_pcie_en>;
91 pinctrl-names = "default";
92 startup-delay-us = <200000>;
93 vin-supply = <&vcc5v0_sys>;
94 };
95
96 vcc3v3_mini_pcie: vcc3v3-mini-pcie-regulator {
97 compatible = "regulator-fixed";
98 regulator-name = "minipcie_3v3";
99 enable-active-high;
100 regulator-min-microvolt = <3300000>;
101 regulator-max-microvolt = <3300000>;
102 gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
103 pinctrl-0 = <&vcc3v3_mini_pcie_en>;
104 pinctrl-names = "default";
105 startup-delay-us = <5000>;
106 vin-supply = <&vcc5v0_sys>;
107 };
108
109 vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
110 compatible = "regulator-fixed";
111 regulator-name = "vcc5v0_usb20_host";
112 enable-active-high;
113 gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
114 pinctrl-0 = <&vcc5v0_usb20_host_en>;
115 pinctrl-names = "default";
116 };
117
118 vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
119 compatible = "regulator-fixed";
120 regulator-name = "vcc5v0_usb30_host";
121 enable-active-high;
122 gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
123 pinctrl-0 = <&vcc5v0_usb30_host_en>;
124 pinctrl-names = "default";
125 };
126
127 vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator {
128 compatible = "regulator-fixed";
129 regulator-name = "vcc5v0_otg_vbus";
130 enable-active-high;
131 regulator-min-microvolt = <5000000>;
132 regulator-max-microvolt = <5000000>;
133 gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
134 pinctrl-0 = <&vcc5v0_otg_vbus_en>;
135 pinctrl-names = "default";
136 };
137};
138
139&combphy0 {
140 status = "okay";
141};
142
143&combphy1 {
144 status = "okay";
145};
146
147&combphy2 {
148 status = "okay";
149};
150
151&cpu0 {
152 cpu-supply = <&vdd_cpu>;
153};
154
155&cpu1 {
156 cpu-supply = <&vdd_cpu>;
157};
158
159&cpu2 {
160 cpu-supply = <&vdd_cpu>;
161};
162
163&cpu3 {
164 cpu-supply = <&vdd_cpu>;
165};
166
167&gpu {
168 mali-supply = <&vdd_gpu>;
169 status = "okay";
170};
171
172&hdmi {
173 avdd-0v9-supply = <&vdda0v9_image>;
174 avdd-1v8-supply = <&vcca1v8_image>;
175 status = "okay";
176};
177
178&hdmi_in {
179 hdmi_in_vp0: endpoint {
180 remote-endpoint = <&vp0_out_hdmi>;
181 };
182};
183
184&hdmi_out {
185 hdmi_out_con: endpoint {
186 remote-endpoint = <&hdmi_con_in>;
187 };
188};
189
190&hdmi_sound {
191 status = "okay";
192};
193
194&i2c0 {
195 status = "okay";
196
197 vdd_cpu: regulator@1c {
198 compatible = "tcs,tcs4525";
199 reg = <0x1c>;
200 fcs,suspend-voltage-selector = <1>;
201 regulator-name = "vdd_cpu";
202 regulator-always-on;
203 regulator-boot-on;
204 regulator-min-microvolt = <800000>;
205 regulator-max-microvolt = <1150000>;
206 regulator-ramp-delay = <2300>;
207 vin-supply = <&vcc5v0_sys>;
208
209 regulator-state-mem {
210 regulator-off-in-suspend;
211 };
212 };
213
214 rk809: pmic@20 {
215 compatible = "rockchip,rk809";
216 reg = <0x20>;
217 interrupt-parent = <&gpio0>;
218 interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
219 assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
220 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
221 #clock-cells = <1>;
222 clock-names = "mclk";
223 clocks = <&cru I2S1_MCLKOUT_TX>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&pmic_int>;
226 rockchip,system-power-controller;
227 #sound-dai-cells = <0>;
228 vcc1-supply = <&vcc3v3_sys>;
229 vcc2-supply = <&vcc3v3_sys>;
230 vcc3-supply = <&vcc3v3_sys>;
231 vcc4-supply = <&vcc3v3_sys>;
232 vcc5-supply = <&vcc3v3_sys>;
233 vcc6-supply = <&vcc3v3_sys>;
234 vcc7-supply = <&vcc3v3_sys>;
235 vcc8-supply = <&vcc3v3_sys>;
236 vcc9-supply = <&vcc3v3_sys>;
237 wakeup-source;
238
239 regulators {
240 vdd_logic: DCDC_REG1 {
241 regulator-name = "vdd_logic";
242 regulator-always-on;
243 regulator-boot-on;
244 regulator-min-microvolt = <500000>;
245 regulator-max-microvolt = <1350000>;
Andy Yanb352c842023-08-05 20:00:11 +0800[diff] [blame]246 regulator-ramp-delay = <6001>;
247 regulator-initial-mode = <0x2>;
248
249 regulator-state-mem {
250 regulator-off-in-suspend;
251 };
252 };
253
254 vdd_gpu: DCDC_REG2 {
255 regulator-name = "vdd_gpu";
256 regulator-always-on;
257 regulator-boot-on;
258 regulator-min-microvolt = <500000>;
259 regulator-max-microvolt = <1350000>;
Andy Yanb352c842023-08-05 20:00:11 +0800[diff] [blame]260 regulator-ramp-delay = <6001>;
261 regulator-initial-mode = <0x2>;
262
263 regulator-state-mem {
264 regulator-off-in-suspend;
265 };
266 };
267
268 vcc_ddr: DCDC_REG3 {
269 regulator-name = "vcc_ddr";
270 regulator-always-on;
271 regulator-boot-on;
272 regulator-initial-mode = <0x2>;
273
274 regulator-state-mem {
275 regulator-on-in-suspend;
276 };
277 };
278
279 vdd_npu: DCDC_REG4 {
280 regulator-name = "vdd_npu";
281 regulator-always-on;
282 regulator-boot-on;
283 regulator-min-microvolt = <500000>;
284 regulator-max-microvolt = <1350000>;
Andy Yanb352c842023-08-05 20:00:11 +0800[diff] [blame]285 regulator-ramp-delay = <6001>;
286 regulator-initial-mode = <0x2>;
287
288 regulator-state-mem {
289 regulator-off-in-suspend;
290 };
291 };
292
293 vcc_1v8: DCDC_REG5 {
294 regulator-name = "vcc_1v8";
295 regulator-always-on;
296 regulator-boot-on;
297 regulator-min-microvolt = <1800000>;
298 regulator-max-microvolt = <1800000>;
299
300 regulator-state-mem {
301 regulator-off-in-suspend;
302 };
303 };
304
305 vdda0v9_image: LDO_REG1 {
306 regulator-name = "vdda0v9_image";
307 regulator-boot-on;
308 regulator-always-on;
309 regulator-min-microvolt = <900000>;
310 regulator-max-microvolt = <900000>;
311
312 regulator-state-mem {
313 regulator-off-in-suspend;
314 };
315 };
316
317 vdda_0v9: LDO_REG2 {
318 regulator-name = "vdda_0v9";
319 regulator-always-on;
320 regulator-boot-on;
321 regulator-min-microvolt = <900000>;
322 regulator-max-microvolt = <900000>;
323
324 regulator-state-mem {
325 regulator-off-in-suspend;
326 };
327 };
328
329 vdda0v9_pmu: LDO_REG3 {
330 regulator-name = "vdda0v9_pmu";
331 regulator-always-on;
332 regulator-boot-on;
333 regulator-min-microvolt = <900000>;
334 regulator-max-microvolt = <900000>;
335
336 regulator-state-mem {
337 regulator-on-in-suspend;
338 regulator-suspend-microvolt = <900000>;
339 };
340 };
341
342 vccio_acodec: LDO_REG4 {
343 regulator-name = "vccio_acodec";
344 regulator-always-on;
345 regulator-boot-on;
346 regulator-min-microvolt = <3300000>;
347 regulator-max-microvolt = <3300000>;
348
349 regulator-state-mem {
350 regulator-off-in-suspend;
351 };
352 };
353
354 vccio_sd: LDO_REG5 {
355 regulator-name = "vccio_sd";
356 regulator-always-on;
357 regulator-boot-on;
358 regulator-min-microvolt = <1800000>;
359 regulator-max-microvolt = <3300000>;
360
361 regulator-state-mem {
362 regulator-off-in-suspend;
363 };
364 };
365
366 vcc3v3_pmu: LDO_REG6 {
367 regulator-name = "vcc3v3_pmu";
368 regulator-always-on;
369 regulator-boot-on;
370 regulator-min-microvolt = <3300000>;
371 regulator-max-microvolt = <3300000>;
372
373 regulator-state-mem {
374 regulator-on-in-suspend;
375 regulator-suspend-microvolt = <3300000>;
376 };
377 };
378
379 vcca_1v8: LDO_REG7 {
380 regulator-name = "vcca_1v8";
381 regulator-always-on;
382 regulator-boot-on;
383 regulator-min-microvolt = <1800000>;
384 regulator-max-microvolt = <1800000>;
385
386 regulator-state-mem {
387 regulator-off-in-suspend;
388 };
389 };
390
391 vcca1v8_pmu: LDO_REG8 {
392 regulator-name = "vcca1v8_pmu";
393 regulator-always-on;
394 regulator-boot-on;
395 regulator-min-microvolt = <1800000>;
396 regulator-max-microvolt = <1800000>;
397
398 regulator-state-mem {
399 regulator-on-in-suspend;
400 regulator-suspend-microvolt = <1800000>;
401 };
402 };
403
404 vcca1v8_image: LDO_REG9 {
405 regulator-name = "vcca1v8_image";
406 regulator-always-on;
407 regulator-boot-on;
408 regulator-min-microvolt = <1800000>;
409 regulator-max-microvolt = <1800000>;
410
411 regulator-state-mem {
412 regulator-off-in-suspend;
413 };
414 };
415
416 vcc_3v3: SWITCH_REG1 {
417 regulator-name = "vcc_3v3";
418 regulator-always-on;
419 regulator-boot-on;
420
421 regulator-state-mem {
422 regulator-off-in-suspend;
423 };
424 };
425
426 vcc3v3_sd: SWITCH_REG2 {
427 regulator-name = "vcc3v3_sd";
428 regulator-always-on;
429 regulator-boot-on;
430
431 regulator-state-mem {
432 regulator-off-in-suspend;
433 };
434 };
435 };
436 };
437};
438
439&i2s1_8ch {
440 rockchip,trcm-sync-tx-only;
441 status = "okay";
442};
443
444&gmac0 {
445 phy-mode = "rgmii";
446 clock_in_out = "output";
447
448 snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
449 snps,reset-active-low;
450 /* Reset time is 20ms, 100ms for rtl8211f */
451 snps,reset-delays-us = <0 20000 100000>;
452
453 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
454 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
455
456 pinctrl-names = "default";
457 pinctrl-0 = <&gmac0_miim
458 &gmac0_tx_bus2
459 &gmac0_rx_bus2
460 &gmac0_rgmii_clk
461 &gmac0_rgmii_bus>;
462
463 tx_delay = <0x22>;
464 rx_delay = <0x0e>;
465
466 phy-handle = <&rgmii_phy0>;
467 status = "okay";
468};
469
470&mdio0 {
471 rgmii_phy0: phy@0 {
472 compatible = "ethernet-phy-ieee802.3-c22";
473 reg = <0x0>;
474 };
475};
476
477&gmac1 {
478 phy-mode = "rgmii";
479 clock_in_out = "output";
480
481 snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
482 snps,reset-active-low;
483 /* Reset time is 20ms, 100ms for rtl8211f */
484 snps,reset-delays-us = <0 20000 100000>;
485
486 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
487 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
488
489 pinctrl-names = "default";
490 pinctrl-0 = <&gmac1m1_miim
491 &gmac1m1_tx_bus2
492 &gmac1m1_rx_bus2
493 &gmac1m1_rgmii_clk
494 &gmac1m1_rgmii_bus>;
495
496 tx_delay = <0x21>;
497 rx_delay = <0x0e>;
498
499 phy-handle = <&rgmii_phy1>;
500 status = "okay";
501};
502
503&mdio1 {
504 rgmii_phy1: phy@0 {
505 compatible = "ethernet-phy-ieee802.3-c22";
506 reg = <0x0>;
507 };
508};
509
510&gic {
511 mbi-ranges = <94 31>, <229 31>, <289 31>;
512};
513
514&pcie30phy {
515 status = "okay";
516};
517
518&pcie3x2 {
519 reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
520 vpcie3v3-supply = <&vcc3v3_m2_pcie>;
521 status = "okay";
522};
523
524&pcie2x1 {
525 reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
526 disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
527 vpcie3v3-supply = <&vcc3v3_mini_pcie>;
528 status = "okay";
529};
530
531&pmu_io_domains {
532 pmuio2-supply = <&vcc3v3_pmu>;
533 vccio1-supply = <&vccio_acodec>;
534 vccio3-supply = <&vccio_sd>;
535 vccio4-supply = <&vcc_1v8>;
536 vccio5-supply = <&vcc_3v3>;
537 vccio6-supply = <&vcc_1v8>;
538 vccio7-supply = <&vcc_3v3>;
539 status = "okay";
540};
541
542&pwm8 {
543 status = "okay";
544};
545
546&pwm9 {
547 status = "disabled";
548};
549
550&pwm10 {
551 status = "disabled";
552};
553
554&pwm14 {
555 status = "disabled";
556};
557
558&spi3 {
559 pinctrl-0 = <&spi3m1_pins>;
560 status = "disabled";
561};
562
563&uart2 {
564 status = "okay";
565};
566
567&uart3 {
568 pinctrl-names = "default";
569 pinctrl-0 = <&uart3m1_xfer>;
570 status = "disabled";
571};
572
573&saradc {
574 vref-supply = <&vcca_1v8>;
575 status = "okay";
576};
577
578&tsadc {
579 rockchip,hw-tshut-mode = <1>;
580 rockchip,hw-tshut-polarity = <0>;
581 status = "okay";
582};
583
584&sdhci {
585 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
586 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
587 bus-width = <8>;
588 max-frequency = <200000000>;
589 mmc-hs200-1_8v;
590 non-removable;
591 pinctrl-names = "default";
592 pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
593 supports-emmc;
594 status = "okay";
595};
596
597&sdmmc0 {
598 max-frequency = <150000000>;
599 no-sdio;
600 no-mmc;
601 bus-width = <4>;
602 cap-mmc-highspeed;
603 cap-sd-highspeed;
604 disable-wp;
605 sd-uhs-sdr104;
606 vmmc-supply = <&vcc3v3_sd>;
607 vqmmc-supply = <&vccio_sd>;
608 pinctrl-names = "default";
609 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
610 status = "okay";
611};
612
613/* USB OTG/USB Host_1 USB 2.0 Comb */
614&usb2phy0 {
615 status = "okay";
616};
617
618&usb2phy0_host {
619 phy-supply = <&vcc5v0_usb30_host>;
620 status = "okay";
621};
622
623&usb2phy0_otg {
624 phy-supply = <&vcc5v0_otg_vbus>;
625 status = "okay";
626};
627
628&usb_host0_ehci {
629 status = "okay";
630};
631
632&usb_host0_ohci {
633 status = "okay";
634};
635
636/* USB Host_2/USB Host_3 USB 2.0 Comb */
637&usb2phy1 {
638 status = "okay";
639};
640
641&usb2phy1_host {
642 status = "okay";
643};
644
645&usb2phy1_otg {
646 phy-supply = <&vcc5v0_usb20_host>;
647 status = "okay";
648};
649
650&usb_host1_ehci {
651 status = "okay";
652};
653
654&usb_host1_ohci {
655 status = "okay";
656};
657
658/* MULTI_PHY0 For SATA0, USB3.0 OTG Only USB2.0 */
659&usb_host0_xhci {
660 phys = <&usb2phy0_otg>;
661 phy-names = "usb2-phy";
662 extcon = <&usb2phy0>;
663 maximum-speed = "high-speed";
664 dr_mode = "host";
665 status = "okay";
666};
667
668&sata0 {
669 status = "okay";
670};
671
672/* USB3.0 Host */
673&usb_host1_xhci {
674 status = "okay";
675};
676
677&vop {
678 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
679 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
680 status = "okay";
681};
682
683&vop_mmu {
684 status = "okay";
685};
686
687&vp0 {
688 vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
689 reg = <ROCKCHIP_VOP2_EP_HDMI0>;
690 remote-endpoint = <&hdmi_in_vp0>;
691 };
692};
693
694&pinctrl {
695 leds {
696 user_led_pin: user-status-led-pin {
697 rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
698 };
699 };
700
701 usb {
702 vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
703 rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
704 };
705
706 vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
707 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
708 };
709
710 vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en {
711 rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
712 };
713 };
714
715 pcie {
716 vcc3v3_m2_pcie_en: vcc3v3-m2-pcie-en {
717 rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
718 };
719
720 vcc3v3_mini_pcie_en: vcc3v3-mini-pcie-en {
721 rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
722 };
723 };
724
725 pmic {
726 pmic_int: pmic-int {
727 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
728 };
729 };
730};