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git01.mediatek.com / filogic / uboot / 75574053c5c09c34d41ffc16013858ffceadc650 / . / doc / README.mpc85xxcds
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wdenk0aeb8532004-10-10 21:21:55 +0000[diff] [blame]1Motorola MPC85xxCDS boards
2--------------------------
3
4The CDS family of boards consists of a PCI backplane called the
5"Arcadia", a PCI-form-factor carrier card that plugs into a PCI slot,
6and a CPU daughter card that bolts onto the daughter card.
7
8Much of the content of the README.mpc85xxads for the 85xx ADS boards
wdenkef3386f2004-10-10 21:27:30 +0000[diff] [blame]9applies to the 85xx CDS boards as well. In particular the toolchain,
wdenk0aeb8532004-10-10 21:21:55 +0000[diff] [blame]10the switch nomenclature, and the basis for the memory map. There are
11some differences, though.
12
13
14Building U-Boot
15---------------
16
17The Binutils in current ELDK toolchain will not support MPC85xx
18chip. You need to use binutils-2.14.tar.bz2 (or newer) from
19 http://ftp.gnu.org/gnu/binutils.
20
21The 85xx CDS code base is known to compile using:
22 gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a)
23
24
25Memory Map
26----------
27
Bin Meng75574052016-02-05 19:30:11 -0800[diff] [blame^]28The memory map for U-Boot and linux has been extended w.r.t. the ADS
wdenk0aeb8532004-10-10 21:21:55 +0000[diff] [blame]29platform to allow for utilization of all 85xx CDS devices. The memory
30map is setup for linux to operate properly. The linux source when
31configured for MPC85xx CDS has been updated to reflect the new memory
32map.
33
34The mapping is:
35
wdenkef3386f2004-10-10 21:27:30 +0000[diff] [blame]36 0x0000_0000 0x7fff_ffff DDR 2G
37 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
38 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
39 0xe000_0000 0xe00f_ffff CCSR 1M
40 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
41 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
42 0xf000_0000 0xf7ff_ffff SDRAM 128M
43 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
44 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
45 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
wdenk0aeb8532004-10-10 21:21:55 +0000[diff] [blame]46
47 (*) The system control registers (CADMUS) start at offset 0xfdb0_4000
48 within the NVRAM/CADMUS region of memory.
49
50
51Using Flash
52-----------
53
54The CDS board has two flash banks, each 8MB in size (2^23 = 0x00800000).
55There is a switch which allows the boot-bank to be selected. The switch
56settings for updating flash are given below.
57
Bin Meng75574052016-02-05 19:30:11 -0800[diff] [blame^]58The U-Boot commands for copying the boot-bank into the secondary bank are
wdenk0aeb8532004-10-10 21:21:55 +0000[diff] [blame]59as follows:
60
61 erase ff780000 ff7fffff
62 cp.b fff80000 ff780000 80000
63
64
Bin Meng75574052016-02-05 19:30:11 -0800[diff] [blame^]65U-Boot/kermit commands for downloading an image, then copying
wdenk0aeb8532004-10-10 21:21:55 +0000[diff] [blame]66it into the secondary bank:
67
68 loadb
69 [Drop to kermit:
wdenkef3386f2004-10-10 21:27:30 +0000[diff] [blame]70 ^\c
71 send <u-boot-bin-image>
72 c
wdenk0aeb8532004-10-10 21:21:55 +0000[diff] [blame]73 ]
74
75 erase ff780000 ff7fffff
76 cp.b $loadaddr ff780000 80000
77
78
Bin Meng75574052016-02-05 19:30:11 -0800[diff] [blame^]79U-Boot commands for downloading an image via tftp and flashing
wdenk0aeb8532004-10-10 21:21:55 +0000[diff] [blame]80it into the second bank:
81
82 tftp 10000 <u-boot.bin.image>
83 erase ff780000 ff7fffff
84 cp.b 10000 ff780000 80000
85
86
87After copying the image into the second bank of flash, be sure to toggle
88SW2[2] on the carrier card before resetting the board in order to set the
89secondary bank as the boot-bank.
90
91
92Carrier Board Switches
93----------------------
94
95As a reminder, you should read the README.mpc85xxads too.
96
97Most switches on the carrier board should not be changed. The only
98user-settable switches on the carrier board are used to configure
99the flash banks and determining the PCI slot.
100
101The first two bits of SW2 control how flash is used on the board:
102
103 12345678
104 --------
wdenkef3386f2004-10-10 21:27:30 +0000[diff] [blame]105 SW2=00XXXXXX FLASH: Boot bank 1, bank 2 available.
106 01XXXXXX FLASH: Boot bank 2, bank 1 available (swapped).
107 10XXXXXX FLASH: Boot promjet, bank 1 available
108 11XXXXXX FLASH: Boot promjet, bank 2 available
wdenk0aeb8532004-10-10 21:21:55 +0000[diff] [blame]109
110The boot bank is always mapped to FF80_0000 and listed first by
111the "flinfo" command. The secondary bank is always FF00_0000.
112
113When using PCI, linux needs to know to which slot the CDS carrier is
114connected.. By convention, the user-specific bits of SW2 are used to
115convey this information:
116
117 12345678
118 --------
wdenkef3386f2004-10-10 21:27:30 +0000[diff] [blame]119 SW2=xxxxxx00 PCI SLOT INFORM: The CDS carrier is in slot0 of the Arcadia
120 xxxxxx01 PCI SLOT INFORM: The CDS carrier is in slot1 of the Arcadia
121 xxxxxx10 PCI SLOT INFORM: The CDS carrier is in slot2 of the Arcadia
122 xxxxxx11 PCI SLOT INFORM: The CDS carrier is in slot3 of the Arcadia
wdenk0aeb8532004-10-10 21:21:55 +0000[diff] [blame]123
124These are cleverly, er, clearly silkscreened as Slot 1 through 4,
125respectively, on the Arcadia near the support posts.
126
127
128The default setting of all switches on the carrier board is:
129
130 12345678
131 --------
132 SW1=01101100
wdenkef3386f2004-10-10 21:27:30 +0000[diff] [blame]133 SW2=0x1111yy x=Flash bank, yy=PCI slot
wdenk0aeb8532004-10-10 21:21:55 +0000[diff] [blame]134 SW3=11101111
135 SW4=10001000
136
137
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500[diff] [blame]1388555/41 CPU Card Switches
139-------------------------
wdenk0aeb8532004-10-10 21:21:55 +0000[diff] [blame]140
141Most switches on the CPU Card should not be changed. However, the
142frequency can be changed by setting SW3:
143
144 12345678
145 --------
146 SW3=XX00XXXX == CORE:CCB 2:1
147 XX01XXXX == CORE:CCB 5:2
148 XX10XXXX == CORE:CCB 3:1
149 XX11XXXX == CORE:CCB 7:2
150 XXXX1000 == CCB:SYSCLK 8:1
151 XXXX1010 == CCB:SYSCLK 10:1
152
153A safe default setting for all switches on the CPU board is:
154
155 12345678
156 --------
157 SW1=10001111
158 SW2=01000111
159 SW3=00001000
160 SW4=11111110
161
162
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500[diff] [blame]1638548 CPU Card Switches
164----------------------
165And, just to be confusing, in this set of switches:
166
167 ON = 1
168 OFF = 0
169
170Default
171 SW1=11111101
172 SW2=10011111
173 SW3=11001000 (8X) (2:1)
174 SW4=11110011
175
176 SW3=X000XXXX == CORE:CCB 4:1
177 X001XXXX == CORE:CCB 9:2
178 X010XXXX == CORE:CCB 1:1
179 X011XXXX == CORE:CCB 3:2
180 X100XXXX == CORE:CCB 2:1
181 X101XXXX == CORE:CCB 5:2
182 X110XXXX == CORE:CCB 3:1
183 X111XXXX == CORE:CCB 7:2
184 XXXX0000 == CCB:SYSCLK 16:1
185 XXXX0001 == RESERVED
186 XXXX0010 == CCB:SYSCLK 2:1
187 XXXX0011 == CCB:SYSCLK 3:1
188 XXXX0100 == CCB:SYSCLK 4:1
189 XXXX0101 == CCB:SYSCLK 5:1
190 XXXX0110 == CCB:SYSCLK 6:1
191 XXXX0111 == RESERVED
192 XXXX1000 == CCB:SYSCLK 8:1
193 XXXX1001 == CCB:SYSCLK 9:1
194 XXXX1010 == CCB:SYSCLK 10:1
195 XXXX1011 == RESERVED
196 XXXX1100 == CCB:SYSCLK 12:1
197 XXXX1101 == CCB:SYSCLK 20:1
198 XXXX1110 == RESERVED
199 XXXX1111 == RESERVED
200
201
wdenk0aeb8532004-10-10 21:21:55 +0000[diff] [blame]202eDINK Info
203----------
204
205One bank of flash may contain an eDINK image.
206
207Memory Map:
208
209 CCSRBAR @ 0xe0000000
210 Flash Bank 1 @ 0xfe000000
211 Flash Bank 2 @ 0xff000000
212 Ram @ 0
213
Bin Meng75574052016-02-05 19:30:11 -0800[diff] [blame^]214Commands for downloading a U-Boot image to memory from edink:
wdenk0aeb8532004-10-10 21:21:55 +0000[diff] [blame]215
216 env -c
217 time -s 4/8/2004 4:30p
218 dl -k -b -o 100000
219 [Drop to kermit:
wdenkef3386f2004-10-10 21:27:30 +0000[diff] [blame]220 ^\c
221 transmit /binary <u-boot-bin-image>
222 c
wdenk0aeb8532004-10-10 21:21:55 +0000[diff] [blame]223 ]
224
225 fu -l 100000 fe780000 80000