blob: fee24e2b5f571023df87b046934c494a63ab7807 [file] [log] [blame]
Adrian Alonso98810772015-09-03 11:49:28 -05001/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <asm/arch/clock.h>
8#include <asm/arch/imx-regs.h>
9#include <asm/arch/mx7-pins.h>
10#include <asm/arch/sys_proto.h>
11#include <asm/gpio.h>
12#include <asm/imx-common/iomux-v3.h>
Adrian Alonso98810772015-09-03 11:49:28 -050013#include <asm/io.h>
14#include <linux/sizes.h>
15#include <common.h>
16#include <fsl_esdhc.h>
17#include <mmc.h>
18#include <miiphy.h>
19#include <netdev.h>
20#include <power/pmic.h>
21#include <power/pfuze3000_pmic.h>
22#include "../common/pfuze.h"
23#include <i2c.h>
24#include <asm/imx-common/mxc_i2c.h>
25#include <asm/arch/crm_regs.h>
Fabio Estevam4ac44192015-09-13 13:06:44 -030026#include <usb/ehci-fsl.h>
Adrian Alonso98810772015-09-03 11:49:28 -050027
28DECLARE_GLOBAL_DATA_PTR;
29
30#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
31 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
32
33#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
34 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
35
36#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
37#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
38
39#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
40
41#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
42 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
43
Peng Fan55be1ed2015-10-29 15:54:53 +080044#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
45 PAD_CTL_DSE_3P3V_49OHM)
46
Peng Fan7431e702015-11-30 17:45:02 +080047#define QSPI_PAD_CTRL \
48 (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
49
Peng Fan62f92602015-12-22 17:04:24 +080050#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
51
52#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
Adrian Alonso98810772015-09-03 11:49:28 -050053#ifdef CONFIG_SYS_I2C_MXC
54#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
55/* I2C1 for PMIC */
Fabio Estevam0344d9c2015-09-13 13:06:42 -030056static struct i2c_pads_info i2c_pad_info1 = {
Adrian Alonso98810772015-09-03 11:49:28 -050057 .scl = {
58 .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
59 .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
60 .gp = IMX_GPIO_NR(4, 8),
61 },
62 .sda = {
63 .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
64 .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
65 .gp = IMX_GPIO_NR(4, 9),
66 },
67};
68#endif
69
70int dram_init(void)
71{
72 gd->ram_size = PHYS_SDRAM_SIZE;
73
74 return 0;
75}
76
77static iomux_v3_cfg_t const wdog_pads[] = {
78 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
79};
80
81static iomux_v3_cfg_t const uart1_pads[] = {
82 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
83 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
84};
85
86static iomux_v3_cfg_t const usdhc1_pads[] = {
87 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93
94 MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96};
97
98static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
99 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110
111 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
112};
113
114#define IOX_SDI IMX_GPIO_NR(1, 9)
115#define IOX_STCP IMX_GPIO_NR(1, 12)
116#define IOX_SHCP IMX_GPIO_NR(1, 13)
117
118static iomux_v3_cfg_t const iox_pads[] = {
119 /* IOX_SDI */
120 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
121 /* IOX_STCP */
122 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
123 /* IOX_SHCP */
124 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
125};
126
127/*
128 * PCIE_DIS_B --> Q0
129 * PCIE_RST_B --> Q1
130 * HDMI_RST_B --> Q2
131 * PERI_RST_B --> Q3
132 * SENSOR_RST_B --> Q4
133 * ENET_RST_B --> Q5
134 * PERI_3V3_EN --> Q6
135 * LCD_PWR_EN --> Q7
136 */
137enum qn {
138 PCIE_DIS_B,
139 PCIE_RST_B,
140 HDMI_RST_B,
141 PERI_RST_B,
142 SENSOR_RST_B,
143 ENET_RST_B,
144 PERI_3V3_EN,
145 LCD_PWR_EN,
146};
147
148enum qn_func {
149 qn_reset,
150 qn_enable,
151 qn_disable,
152};
153
154enum qn_level {
155 qn_low = 0,
156 qn_high = 1,
157};
158
159static enum qn_level seq[3][2] = {
160 {0, 1}, {1, 1}, {0, 0}
161};
162
163static enum qn_func qn_output[8] = {
164 qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable,
165 qn_enable
166};
167
Fabio Estevam0344d9c2015-09-13 13:06:42 -0300168static void iox74lv_init(void)
Adrian Alonso98810772015-09-03 11:49:28 -0500169{
170 int i;
171
172 for (i = 7; i >= 0; i--) {
173 gpio_direction_output(IOX_SHCP, 0);
174 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
175 udelay(500);
176 gpio_direction_output(IOX_SHCP, 1);
177 udelay(500);
178 }
179
180 gpio_direction_output(IOX_STCP, 0);
181 udelay(500);
182 /*
183 * shift register will be output to pins
184 */
185 gpio_direction_output(IOX_STCP, 1);
186
187 for (i = 7; i >= 0; i--) {
188 gpio_direction_output(IOX_SHCP, 0);
189 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
190 udelay(500);
191 gpio_direction_output(IOX_SHCP, 1);
192 udelay(500);
193 }
194 gpio_direction_output(IOX_STCP, 0);
195 udelay(500);
196 /*
197 * shift register will be output to pins
198 */
199 gpio_direction_output(IOX_STCP, 1);
200};
201
Peng Fan62f92602015-12-22 17:04:24 +0800202#ifdef CONFIG_NAND_MXS
203static iomux_v3_cfg_t const gpmi_pads[] = {
204 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
205 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
206 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
207 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
208 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
209 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
210 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
211 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
212 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
213 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
214 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
215 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
216 MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
217 MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
218 MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
219 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
220 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
221 MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
222 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
223};
224
225static void setup_gpmi_nand(void)
226{
227 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
228
229 /* NAND_USDHC_BUS_CLK is set in rom */
230 set_clk_nand();
231}
232#endif
233
Peng Fan55be1ed2015-10-29 15:54:53 +0800234#ifdef CONFIG_VIDEO_MXS
235static iomux_v3_cfg_t const lcd_pads[] = {
236 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
237 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
238 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
239 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
240 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
241 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
242 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
243 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
244 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
245 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
246 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
247 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
248 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
249 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
250 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
251 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
252 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
253 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
254 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
255 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
256 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
257 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
258 MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
259 MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
260 MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
261 MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
262 MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
263 MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
264
265 MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
266};
267
268static iomux_v3_cfg_t const pwm_pads[] = {
269 /* Use GPIO for Brightness adjustment, duty cycle = period */
270 MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
271};
272
273static int setup_lcd(void)
274{
275 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
276
277 imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
278
279 /* Reset LCD */
280 gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
281 udelay(500);
282 gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
283
284 /* Set Brightness to high */
285 gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
286
287 return 0;
288}
289#endif
290
Adrian Alonso98810772015-09-03 11:49:28 -0500291#ifdef CONFIG_FEC_MXC
292static iomux_v3_cfg_t const fec1_pads[] = {
293 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
294 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
295 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
296 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
297 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
298 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
299 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
300 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
301 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
302 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
303 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
304 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
305 MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
306 MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
307};
308
309static void setup_iomux_fec(void)
310{
311 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
312}
313#endif
314
315static void setup_iomux_uart(void)
316{
317 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
318}
319
320#ifdef CONFIG_FSL_ESDHC
321
322#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
323#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
324#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
325
326static struct fsl_esdhc_cfg usdhc_cfg[3] = {
327 {USDHC1_BASE_ADDR, 0, 4},
328 {USDHC3_BASE_ADDR},
329};
330
Peng Fan6c9d8fb2016-01-28 16:51:25 +0800331int board_mmc_get_env_dev(int devno)
Adrian Alonso98810772015-09-03 11:49:28 -0500332{
Peng Fan6c9d8fb2016-01-28 16:51:25 +0800333 if (devno == 2)
334 devno--;
Adrian Alonso98810772015-09-03 11:49:28 -0500335
Peng Fan6c9d8fb2016-01-28 16:51:25 +0800336 return devno;
Adrian Alonso98810772015-09-03 11:49:28 -0500337}
338
339static int mmc_map_to_kernel_blk(int dev_no)
340{
341 if (dev_no == 1)
342 dev_no++;
343
344 return dev_no;
345}
346
347int board_mmc_getcd(struct mmc *mmc)
348{
349 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
350 int ret = 0;
351
352 switch (cfg->esdhc_base) {
353 case USDHC1_BASE_ADDR:
354 ret = !gpio_get_value(USDHC1_CD_GPIO);
355 break;
356 case USDHC3_BASE_ADDR:
357 ret = 1; /* Assume uSDHC3 emmc is always present */
358 break;
359 }
360
361 return ret;
362}
363
364int board_mmc_init(bd_t *bis)
365{
366 int i, ret;
367 /*
368 * According to the board_mmc_init() the following map is done:
Bin Meng75574052016-02-05 19:30:11 -0800369 * (U-Boot device node) (Physical Port)
Adrian Alonso98810772015-09-03 11:49:28 -0500370 * mmc0 USDHC1
371 * mmc2 USDHC3 (eMMC)
372 */
373 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
374 switch (i) {
375 case 0:
376 imx_iomux_v3_setup_multiple_pads(
377 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
378 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
379 gpio_direction_input(USDHC1_CD_GPIO);
380 gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
381 gpio_direction_output(USDHC1_PWR_GPIO, 0);
382 udelay(500);
383 gpio_direction_output(USDHC1_PWR_GPIO, 1);
384 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
385 break;
386 case 1:
387 imx_iomux_v3_setup_multiple_pads(
388 usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
389 gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
390 gpio_direction_output(USDHC3_PWR_GPIO, 0);
391 udelay(500);
392 gpio_direction_output(USDHC3_PWR_GPIO, 1);
393 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
394 break;
395 default:
396 printf("Warning: you configured more USDHC controllers"
397 "(%d) than supported by the board\n", i + 1);
398 return -EINVAL;
399 }
400
401 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
402 if (ret)
403 return ret;
404 }
405
406 return 0;
407}
408
409static int check_mmc_autodetect(void)
410{
411 char *autodetect_str = getenv("mmcautodetect");
412
413 if ((autodetect_str != NULL) &&
414 (strcmp(autodetect_str, "yes") == 0)) {
415 return 1;
416 }
417
418 return 0;
419}
420
421static void mmc_late_init(void)
422{
423 char cmd[32];
424 char mmcblk[32];
Peng Fan6c9d8fb2016-01-28 16:51:25 +0800425 u32 dev_no = mmc_get_env_dev();
Adrian Alonso98810772015-09-03 11:49:28 -0500426
427 if (!check_mmc_autodetect())
428 return;
429
430 setenv_ulong("mmcdev", dev_no);
431
432 /* Set mmcblk env */
433 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
434 mmc_map_to_kernel_blk(dev_no));
435 setenv("mmcroot", mmcblk);
436
437 sprintf(cmd, "mmc dev %d", dev_no);
438 run_command(cmd, 0);
439}
440
441#endif
442
443#ifdef CONFIG_FEC_MXC
444int board_eth_init(bd_t *bis)
445{
446 int ret;
447
448 setup_iomux_fec();
449
450 ret = fecmxc_initialize_multi(bis, 0,
451 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
452 if (ret)
453 printf("FEC1 MXC: %s:failed\n", __func__);
454
455 return ret;
456}
457
458static int setup_fec(void)
459{
460 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
461 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
462
463 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
464 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
465 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
466 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
467
468 return set_clk_enet(ENET_125MHz);
469}
470
471
472int board_phy_config(struct phy_device *phydev)
473{
474 /* enable rgmii rxc skew and phy mode select to RGMII copper */
475 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
476 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
477 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
478 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
479
480 if (phydev->drv->config)
481 phydev->drv->config(phydev);
482 return 0;
483}
484#endif
485
Peng Fan7431e702015-11-30 17:45:02 +0800486#ifdef CONFIG_FSL_QSPI
487static iomux_v3_cfg_t const quadspi_pads[] = {
488 MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
489 MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
490 MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
491 MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
492 MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
493 MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
494};
495
496int board_qspi_init(void)
497{
498 /* Set the iomux */
499 imx_iomux_v3_setup_multiple_pads(quadspi_pads,
500 ARRAY_SIZE(quadspi_pads));
501
502 /* Set the clock */
503 set_clk_qspi();
504
505 return 0;
506}
507#endif
508
Adrian Alonso98810772015-09-03 11:49:28 -0500509int board_early_init_f(void)
510{
511 setup_iomux_uart();
512
513 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
514
515 return 0;
516}
517
518int board_init(void)
519{
520 /* address of boot parameters */
521 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
522
523 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
524
525 iox74lv_init();
526
527#ifdef CONFIG_FEC_MXC
528 setup_fec();
529#endif
530
Peng Fan62f92602015-12-22 17:04:24 +0800531#ifdef CONFIG_NAND_MXS
532 setup_gpmi_nand();
533#endif
534
Peng Fan55be1ed2015-10-29 15:54:53 +0800535#ifdef CONFIG_VIDEO_MXS
536 setup_lcd();
537#endif
538
Peng Fan7431e702015-11-30 17:45:02 +0800539#ifdef CONFIG_FSL_QSPI
540 board_qspi_init();
541#endif
542
Adrian Alonso98810772015-09-03 11:49:28 -0500543 return 0;
544}
545
Adrian Alonso98810772015-09-03 11:49:28 -0500546#ifdef CONFIG_POWER
547#define I2C_PMIC 0
548int power_init_board(void)
549{
550 struct pmic *p;
551 int ret;
552 unsigned int reg, rev_id;
553
554 ret = power_pfuze3000_init(I2C_PMIC);
555 if (ret)
556 return ret;
557
558 p = pmic_get("PFUZE3000");
559 ret = pmic_probe(p);
560 if (ret)
561 return ret;
562
563 pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
564 pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
565 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
566
567 /* disable Low Power Mode during standby mode */
568 pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
569 reg |= 0x1;
570 pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
571
572 return 0;
573}
574#endif
575
576int board_late_init(void)
577{
Peng Fan6b7c3dc2015-09-14 13:34:45 +0800578 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
579
Adrian Alonso98810772015-09-03 11:49:28 -0500580#ifdef CONFIG_ENV_IS_IN_MMC
581 mmc_late_init();
582#endif
583
584 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
585
Peng Fan6b7c3dc2015-09-14 13:34:45 +0800586 set_wdog_reset(wdog);
587
588 /*
589 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
590 * since we use PMIC_PWRON to reset the board.
591 */
592 clrsetbits_le16(&wdog->wcr, 0, 0x10);
Adrian Alonso98810772015-09-03 11:49:28 -0500593
594 return 0;
595}
596
Adrian Alonso98810772015-09-03 11:49:28 -0500597int checkboard(void)
598{
599 puts("Board: i.MX7D SABRESD\n");
600
601 return 0;
602}
603
604#ifdef CONFIG_USB_EHCI_MX7
Fabio Estevam0344d9c2015-09-13 13:06:42 -0300605static iomux_v3_cfg_t const usb_otg1_pads[] = {
Adrian Alonso98810772015-09-03 11:49:28 -0500606 MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
607};
608
Fabio Estevam0344d9c2015-09-13 13:06:42 -0300609static iomux_v3_cfg_t const usb_otg2_pads[] = {
Adrian Alonso98810772015-09-03 11:49:28 -0500610 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
611};
612
613int board_ehci_hcd_init(int port)
614{
615 switch (port) {
616 case 0:
617 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
618 ARRAY_SIZE(usb_otg1_pads));
619 break;
620 case 1:
621 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
622 ARRAY_SIZE(usb_otg2_pads));
623 break;
624 default:
625 printf("MXC USB port %d not yet supported\n", port);
626 return -EINVAL;
627 }
628 return 0;
629}
630#endif