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git01.mediatek.com / filogic / uboot / 754f55e4b04e5048f4e886bf78ca2ea01df2fa67 / . / configs / chromebook_jerry_defconfig
blob: 27e53c14c6c21cb6ac9eaebb08b04f6f2dbd156d [file] [log] [blame]
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
3CONFIG_SYS_MALLOC_F_LEN=0x2000
4CONFIG_ROCKCHIP_RK3288=y
5CONFIG_TARGET_CHROMEBOOK_JERRY=y
Simon Glass94906e42016-01-21 19:45:17 -0700[diff] [blame]6CONFIG_ROCKCHIP_FAST_SPL=y
Thomas Chou3a077cd2015-11-11 21:39:33 +0800[diff] [blame]7CONFIG_SPL_STACK_R_ADDR=0x80000
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]8CONFIG_DM_KEYBOARD=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]9CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry"
10CONFIG_SPL_STACK_R=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]11CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]12# CONFIG_CMD_IMLS is not set
13# CONFIG_CMD_SETEXPR is not set
14CONFIG_CMD_PMIC=y
15CONFIG_CMD_REGULATOR=y
16CONFIG_SPL_OF_CONTROL=y
Simon Glass8d32f4b2016-01-21 19:43:38 -0700[diff] [blame]17CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]18CONFIG_REGMAP=y
huang lindd8515e2015-11-17 14:20:13 +0800[diff] [blame]19CONFIG_SPL_REGMAP=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]20CONFIG_SYSCON=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]21CONFIG_SPL_SYSCON=y
Simon Glass70bad912016-01-21 19:43:49 -0700[diff] [blame]22# CONFIG_SPL_SIMPLE_BUS is not set
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]23CONFIG_CLK=y
24CONFIG_SPL_CLK=y
25CONFIG_ROCKCHIP_GPIO=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]26CONFIG_I2C_CROS_EC_TUNNEL=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]27CONFIG_SYS_I2C_ROCKCHIP=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]28CONFIG_I2C_MUX=y
29CONFIG_CROS_EC_KEYB=y
30CONFIG_CMD_CROS_EC=y
31CONFIG_CROS_EC=y
32CONFIG_CROS_EC_SPI=y
Simon Glassaf0b7442016-01-21 19:43:36 -0700[diff] [blame]33CONFIG_PWRSEQ=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]34CONFIG_RESET=y
35CONFIG_DM_MMC=y
36CONFIG_ROCKCHIP_DWMMC=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]37CONFIG_PINCTRL=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]38CONFIG_SPL_PINCTRL=y
Simon Glass2ac46482015-12-29 05:22:45 -0700[diff] [blame]39# CONFIG_SPL_PINCTRL_FULL is not set
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]40CONFIG_ROCKCHIP_PINCTRL=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]41CONFIG_DM_PMIC=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]42# CONFIG_SPL_PMIC_CHILDREN is not set
Simon Glass99ac7012016-01-21 19:43:48 -0700[diff] [blame]43CONFIG_PMIC_RK808=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]44CONFIG_DM_REGULATOR=y
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]45CONFIG_DM_REGULATOR_FIXED=y
Simon Glass99ac7012016-01-21 19:43:48 -0700[diff] [blame]46CONFIG_REGULATOR_RK808=y
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]47CONFIG_DM_PWM=y
48CONFIG_PWM_ROCKCHIP=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]49CONFIG_RAM=y
50CONFIG_SPL_RAM=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]51CONFIG_DEBUG_UART=y
52CONFIG_DEBUG_UART_BASE=0xff690000
53CONFIG_DEBUG_UART_CLOCK=24000000
54CONFIG_DEBUG_UART_SHIFT=2
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]55CONFIG_SYS_NS16550=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]56CONFIG_ROCKCHIP_SPI=y
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]57CONFIG_DM_VIDEO=y
58CONFIG_VIDEO_ROTATION=y
59CONFIG_VIDEO_ROCKCHIP=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]60CONFIG_USE_PRIVATE_LIBGCC=y
Simon Glass2ac46482015-12-29 05:22:45 -0700[diff] [blame]61CONFIG_USE_TINY_PRINTF=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]62CONFIG_CMD_DHRYSTONE=y
63CONFIG_ERRNO_STR=y