blob: 159271996b5f2695b3d5ea2b7d5e0d876380b8dd [file] [log] [blame]
Mike Frysinger07f82272008-10-12 21:55:45 -04001/*
2 * U-boot - Configuration file for CM-BF527 board
3 */
4
5#ifndef __CONFIG_CM_BF527_H__
6#define __CONFIG_CM_BF527_H__
7
Mike Frysinger18a407c2009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysinger07f82272008-10-12 21:55:45 -04009
10
11/*
12 * Processor Settings
13 */
14#define CONFIG_BFIN_CPU bf527-0.0
15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 21
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 4
40
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 9
46#define CONFIG_MEM_SIZE 32
47
48#define CONFIG_EBIU_SDRRC_VAL 0x3f8
49#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
50
51#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
52#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
53#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
54
55#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
56#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
57
58
59/*
60 * NAND Settings
61 * (can't be used sametime as ethernet)
62 */
63/* #define CONFIG_BFIN_NFC */
64#ifdef CONFIG_BFIN_NFC
65#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
66#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
67#define CONFIG_SYS_MAX_NAND_DEVICE 1
68#define NAND_MAX_CHIPS 1
69#define CONFIG_CMD_NAND
70#endif
71
72
73/*
74 * Network Settings
75 */
76#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
77 !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
78#define ADI_CMDS_NETWORK 1
79#define CONFIG_BFIN_MAC
80#define CONFIG_RMII
81#define CONFIG_NETCONSOLE 1
82#define CONFIG_NET_MULTI 1
83#endif
84#define CONFIG_HOSTNAME cm-bf527
85/* Uncomment next line to use fixed MAC address */
86/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
87
88
89/*
90 * Flash Settings
91 */
92#define CONFIG_FLASH_CFI_DRIVER
93#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
94#define CONFIG_SYS_FLASH_BASE 0x20000000
95#define CONFIG_SYS_FLASH_CFI
96#define CONFIG_SYS_FLASH_PROTECTION
97#define CONFIG_SYS_MAX_FLASH_BANKS 1
Harald Krapfenbauerb46c3472009-08-18 04:49:57 -040098#define CONFIG_SYS_MAX_FLASH_SECT 67
Mike Frysinger07f82272008-10-12 21:55:45 -040099
100
101/*
102 * Env Storage Settings
103 */
104#define CONFIG_ENV_IS_IN_FLASH 1
105#define CONFIG_ENV_ADDR 0x20008000
106#define CONFIG_ENV_OFFSET 0x8000
107#define CONFIG_ENV_SIZE 0x8000
108#define CONFIG_ENV_SECT_SIZE 0x20000
109#define ENV_IS_EMBEDDED_CUSTOM
110
111
112/*
113 * I2C Settings
114 */
115#define CONFIG_BFIN_TWI_I2C 1
116#define CONFIG_HARD_I2C 1
117#define CONFIG_SYS_I2C_SPEED 50000
118#define CONFIG_SYS_I2C_SLAVE 0
119
120
121/*
122 * Misc Settings
123 */
124#define CONFIG_BAUDRATE 115200
125#define CONFIG_MISC_INIT_R
126#define CONFIG_RTC_BFIN
127#define CONFIG_UART_CONSOLE 0
128
129
130/*
131 * Pull in common ADI header for remaining command/environment setup
132 */
133#include <configs/bfin_adi_common.h>
134
Mike Frysinger07f82272008-10-12 21:55:45 -0400135#endif