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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Kumar Gala2683c532011-04-13 08:37:44 -05002/*
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Kumar Gala2683c532011-04-13 08:37:44 -05004 */
5
6#ifndef __FM_H__
7#define __FM_H__
8
9#include <common.h>
Claudiu Manoilde9ad7a2014-09-05 13:52:36 +080010#include <phy.h>
Kumar Gala2683c532011-04-13 08:37:44 -050011#include <fm_eth.h>
Shaohui Xie513eaf22015-10-26 19:47:47 +080012#include <fsl_fman.h>
Kumar Gala2683c532011-04-13 08:37:44 -050013
14/* Port ID */
15#define OH_PORT_ID_BASE 0x01
16#define MAX_NUM_OH_PORT 7
17#define RX_PORT_1G_BASE 0x08
18#define MAX_NUM_RX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC
19#define RX_PORT_10G_BASE 0x10
Shengzhou Liu4227e492013-11-22 17:39:09 +080020#define RX_PORT_10G_BASE2 0x08
Kumar Gala2683c532011-04-13 08:37:44 -050021#define TX_PORT_1G_BASE 0x28
22#define MAX_NUM_TX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC
23#define TX_PORT_10G_BASE 0x30
Shengzhou Liu4227e492013-11-22 17:39:09 +080024#define TX_PORT_10G_BASE2 0x28
Zhao Qiang1ae99192013-09-04 10:11:27 +080025#define MIIM_TIMEOUT 0xFFFF
Kumar Gala2683c532011-04-13 08:37:44 -050026
27struct fm_muram {
Hou Zhiqiangea52d332015-10-26 19:47:44 +080028 void *base;
29 void *top;
30 size_t size;
31 void *alloc;
Kumar Gala2683c532011-04-13 08:37:44 -050032};
33#define FM_MURAM_RES_SIZE 0x01000
34
35/* Rx/Tx buffer descriptor */
36struct fm_port_bd {
37 u16 status;
38 u16 len;
39 u32 res0;
40 u16 res1;
41 u16 buf_ptr_hi;
42 u32 buf_ptr_lo;
43};
44
45/* Common BD flags */
46#define BD_LAST 0x0800
47
48/* Rx BD status flags */
49#define RxBD_EMPTY 0x8000
50#define RxBD_LAST BD_LAST
51#define RxBD_FIRST 0x0400
52#define RxBD_PHYS_ERR 0x0008
53#define RxBD_SIZE_ERR 0x0004
54#define RxBD_ERROR (RxBD_PHYS_ERR | RxBD_SIZE_ERR)
55
56/* Tx BD status flags */
57#define TxBD_READY 0x8000
58#define TxBD_LAST BD_LAST
59
Madalin Bucurb76b0a62020-04-23 16:25:19 +030060#ifdef CONFIG_DM_ETH
61enum fm_mac_type {
62#ifdef CONFIG_SYS_FMAN_V3
63 FM_MEMAC,
64#else
65 FM_DTSEC,
66 FM_TGEC,
67#endif
68};
69#endif
70
71/* Fman ethernet private struct */
Kumar Gala2683c532011-04-13 08:37:44 -050072/* Rx/Tx queue descriptor */
73struct fm_port_qd {
74 u16 gen;
75 u16 bd_ring_base_hi;
76 u32 bd_ring_base_lo;
77 u16 bd_ring_size;
78 u16 offset_in;
79 u16 offset_out;
80 u16 res0;
81 u32 res1[0x4];
82};
83
84/* IM global parameter RAM */
85struct fm_port_global_pram {
86 u32 mode; /* independent mode register */
87 u32 rxqd_ptr; /* Rx queue descriptor pointer */
88 u32 txqd_ptr; /* Tx queue descriptor pointer */
89 u16 mrblr; /* max Rx buffer length */
90 u16 rxqd_bsy_cnt; /* RxQD busy counter, should be cleared */
91 u32 res0[0x4];
92 struct fm_port_qd rxqd; /* Rx queue descriptor */
93 struct fm_port_qd txqd; /* Tx queue descriptor */
94 u32 res1[0x28];
95};
96
97#define FM_PRAM_SIZE sizeof(struct fm_port_global_pram)
98#define FM_PRAM_ALIGN 256
99#define PRAM_MODE_GLOBAL 0x20000000
100#define PRAM_MODE_GRACEFUL_STOP 0x00800000
101
York Sunab507fb2016-11-16 16:06:48 -0800102#if defined(CONFIG_ARCH_P1023)
Kumar Gala2683c532011-04-13 08:37:44 -0500103#define FM_FREE_POOL_SIZE 0x2000 /* 8K bytes */
104#else
105#define FM_FREE_POOL_SIZE 0x20000 /* 128K bytes */
106#endif
107#define FM_FREE_POOL_ALIGN 256
108
Hou Zhiqiangea52d332015-10-26 19:47:44 +0800109void *fm_muram_alloc(int fm_idx, size_t size, ulong align);
110void *fm_muram_base(int fm_idx);
Kumar Gala2683c532011-04-13 08:37:44 -0500111int fm_init_common(int index, struct ccsr_fman *reg);
112int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info);
113phy_interface_t fman_port_enet_if(enum fm_port port);
Kumar Gala5536d922011-09-14 12:01:35 -0500114void fman_disable_port(enum fm_port port);
Valentin Longchamp51b2ca32013-10-18 11:47:21 +0200115void fman_enable_port(enum fm_port port);
Madalin Bucurb76b0a62020-04-23 16:25:19 +0300116int fman_id(struct udevice *dev);
117void *fman_port(struct udevice *dev, int num);
118#ifdef CONFIG_DM_ETH
119void *fman_mdio(struct udevice *dev, enum fm_mac_type type, int num);
120#endif
Kumar Gala2683c532011-04-13 08:37:44 -0500121
122struct fsl_enet_mac {
123 void *base; /* MAC controller registers base address */
124 void *phyregs;
125 int max_rx_len;
126 void (*init_mac)(struct fsl_enet_mac *mac);
127 void (*enable_mac)(struct fsl_enet_mac *mac);
128 void (*disable_mac)(struct fsl_enet_mac *mac);
129 void (*set_mac_addr)(struct fsl_enet_mac *mac, u8 *mac_addr);
130 void (*set_if_mode)(struct fsl_enet_mac *mac, phy_interface_t type,
131 int speed);
132};
133
134/* Fman ethernet private struct */
135struct fm_eth {
136 int fm_index; /* Fman index */
137 u32 num; /* 0..n-1 for give type */
138 struct fm_bmi_tx_port *tx_port;
139 struct fm_bmi_rx_port *rx_port;
140 enum fm_eth_type type; /* 1G or 10G ethernet */
141 phy_interface_t enet_if;
142 struct fsl_enet_mac *mac; /* MAC controller */
143 struct mii_dev *bus;
144 struct phy_device *phydev;
145 int phyaddr;
Madalin Bucurb76b0a62020-04-23 16:25:19 +0300146#ifndef CONFIG_DM_ETH
Kumar Gala2683c532011-04-13 08:37:44 -0500147 struct eth_device *dev;
Madalin Bucurb76b0a62020-04-23 16:25:19 +0300148#else
149 enum fm_mac_type mac_type;
150 struct udevice *dev;
151 struct udevice *pcs_mdio;
152#endif
Kumar Gala2683c532011-04-13 08:37:44 -0500153 int max_rx_len;
154 struct fm_port_global_pram *rx_pram; /* Rx parameter table */
155 struct fm_port_global_pram *tx_pram; /* Tx parameter table */
156 void *rx_bd_ring; /* Rx BD ring base */
157 void *cur_rxbd; /* current Rx BD */
158 void *rx_buf; /* Rx buffer base */
159 void *tx_bd_ring; /* Tx BD ring base */
160 void *cur_txbd; /* current Tx BD */
161};
162
163#define RX_BD_RING_SIZE 8
164#define TX_BD_RING_SIZE 8
165#define MAX_RXBUF_LOG2 11
166#define MAX_RXBUF_LEN (1 << MAX_RXBUF_LOG2)
167
Rotariu Marian-Cristian092af032014-05-19 10:59:52 +0300168#define PORT_IS_ENABLED(port) (fm_port_to_index(port) == -1 ? \
169 0 : fm_info[fm_port_to_index(port)].enabled)
Shengzhou Liu0348bf82013-03-25 07:39:29 +0000170
Kumar Gala2683c532011-04-13 08:37:44 -0500171#endif /* __FM_H__ */