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git01.mediatek.com / filogic / uboot / 7511d14d5486cf4f75c3fce53adf20201959790a / . / board / overo / overo.h
blob: 513a3e3d632ff1417816ede4d9c40a5b18167b8e [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Dirk Behme220faba2009-01-28 21:39:57 +0100[diff] [blame]2/*
3 * (C) Copyright 2008
4 * Steve Sakoman <steve@sakoman.com>
Dirk Behme220faba2009-01-28 21:39:57 +0100[diff] [blame]5 */
6#ifndef _OVERO_H_
7#define _OVERO_H_
8
9const omap3_sysinfo sysinfo = {
Dirk Behme220faba2009-01-28 21:39:57 +0100[diff] [blame]10 DDR_STACKED,
Dirk Behme220faba2009-01-28 21:39:57 +0100[diff] [blame]11 "Gumstix Overo board",
12#if defined(CONFIG_ENV_IS_IN_ONENAND)
13 "OneNAND",
14#else
15 "NAND",
16#endif
17};
18
Arun Bharadwaj9a0475c2015-04-28 16:55:29 -0700[diff] [blame]19int get_board_revision(void);
20
Andreas Müller785f1f02012-01-04 15:26:25 +0000[diff] [blame]21/* overo revisions */
22#define REVISION_0 0x0
23#define REVISION_1 0x1
24#define REVISION_2 0x2
Steve Sakoman9f32a9e2013-07-24 12:22:34 -0700[diff] [blame]25#define REVISION_3 0x3
Ash Charles9517fbb42014-05-21 14:04:52 -0700[diff] [blame]26#define REVISION_4 0x4
Andreas Müller785f1f02012-01-04 15:26:25 +0000[diff] [blame]27
Dirk Behme220faba2009-01-28 21:39:57 +0100[diff] [blame]28/*
29 * IEN - Input Enable
30 * IDIS - Input Disable
31 * PTD - Pull type Down
32 * PTU - Pull type Up
33 * DIS - Pull type selection is inactive
34 * EN - Pull type selection is active
35 * M0 - Mode 0
36 * The commented string gives the final mux configuration for that pin
37 */
Stefan Herbrechtsmeiere2f29a12014-09-16 17:51:08 +0200[diff] [blame]38#define MUX_GUMSTIX() \
39 /*GPMC*/\
40 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
41 MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
42 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
43 MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
44 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) /*GPIO_63*/\
45 /* - CAM_IRQ*/\
46 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
47 /* - SMSC911X_NRES*/\
48 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
49 /*DSS*/\
50 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
51 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
52 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
53 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
54 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
55 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
56 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
57 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
58 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
59 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
60 MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
61 MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
62 MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
63 MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
64 MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
65 MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
66 MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
67 MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
68 MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
69 MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
70 MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
71 MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
72 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
73 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
74 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
75 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
76 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
77 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
78 /*CAMERA*/\
79 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
80 MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
81 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\
82 MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
83 MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\
84 /* - PEN_DOWN*/\
85 /*Bluetooth*/\
86 MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
87 MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
88 MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
89 MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
90 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
91 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
92 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
93 /*Serial Interface*/\
94 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
95 MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
96 MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
97 MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
98 MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
99 MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
100 MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
101 MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\
102 /* - LAN_INTR */\
103 /*Control and debug */\
104 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\
105 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
106 MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\
107 MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
108 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\
109 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
110 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
111 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
112 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
113 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\
114 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\
115 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\
116
Steve Sakoman541ce992010-08-24 10:37:29 -0700[diff] [blame]117#define MUX_OVERO_SDIO2_DIRECT() \
118 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
119 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
120 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
121 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
122 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
123 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
124 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M0)) /*MMC2_DAT4*/\
125 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M0)) /*MMC2_DAT5*/\
126 MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M0)) /*MMC2_DAT6*/\
127 MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\
128 MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\
129 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\
130 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
131 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
132
133#define MUX_OVERO_SDIO2_TRANSCEIVER() \
134 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
135 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
136 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
137 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
138 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
139 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
140 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
141 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
142 MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
143 MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
144 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) /*GPIO_126*/\
145 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\
146 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
147 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
Olof Johansson4963f922009-09-29 10:22:45 -0400[diff] [blame]148
Steve Sakoman0b880632010-09-20 08:05:14 -0700[diff] [blame]149#define MUX_USRP_E() \
150 MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M4)) /*GPIO_173 */\
151 MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175 */\
152
Ash Charles7baad0f2014-05-21 14:04:53 -0700[diff] [blame]153#define MUX_ALTO35() \
154 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-BTN*/\
155 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M4)) /*GPIO_148-RED LED*/\
156 MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\
157 MUX_VAL(CP(UART1_RX), (IDIS | PTD | DIS | M4)) /*GPIO_151-BLUE LED*/\
158 MUX_VAL(CP(HDQ_SIO), (IDIS | PTD | DIS | M4)) /*GPIO_170-GREEN LED*/\
159 MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175*/\
160
161#define MUX_ARBOR43C() \
162 MUX_VAL(CP(CSI2_DX1), (IDIS | PTD | DIS | M4)) /*GPIO_114-RED LED*/\
163 MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\
164 MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) /*GPIO_170-BUTTON */\
165 MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M4)) /*GPIO_186-BLUE LED*/\
166 MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | DIS | M4)) /*GPIO_31-CAP WAKE*/\
167 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-CAP IRQ*/\
168
Dirk Behme220faba2009-01-28 21:39:57 +0100[diff] [blame]169#endif