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git01.mediatek.com / filogic / uboot / 74edd5cb05f05c2721a722456d7cb579df848981 / . / board / stx / stxxtc / stxxtc.c
blob: 4afbbf509921d6ed9ca53297acc35114e8763575 [file] [log] [blame]
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]1/*
2 * (C) Copyright 2000-2004
3 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2005
6 * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * U-Boot port on STx XTc board
29 * Mostly copied from Netta
30 */
31
32#include <common.h>
33#include <miiphy.h>
34
35#include "mpc8xx.h"
36
37#ifdef CONFIG_HW_WATCHDOG
38#include <watchdog.h>
39#endif
40
41/****************************************************************/
42
43/* some sane bit macros */
44#define _BD(_b) (1U << (31-(_b)))
45#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
46
47#define _BW(_b) (1U << (15-(_b)))
48#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
49
50#define _BB(_b) (1U << (7-(_b)))
51#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
52
53#define _B(_b) _BD(_b)
54#define _BR(_l, _h) _BDR(_l, _h)
55
56/****************************************************************/
57
58/*
59 * Check Board Identity:
60 *
61 * Return 1 always.
62 */
63
64int checkboard(void)
65{
66 printf ("Silicon Turnkey eXpress XTc\n");
67 return (0);
68}
69
70/****************************************************************/
71
72#define _NOT_USED_ 0xFFFFFFFF
73
74/****************************************************************/
75
76#define CS_0000 0x00000000
77#define CS_0001 0x10000000
78#define CS_0010 0x20000000
79#define CS_0011 0x30000000
80#define CS_0100 0x40000000
81#define CS_0101 0x50000000
82#define CS_0110 0x60000000
83#define CS_0111 0x70000000
84#define CS_1000 0x80000000
85#define CS_1001 0x90000000
86#define CS_1010 0xA0000000
87#define CS_1011 0xB0000000
88#define CS_1100 0xC0000000
89#define CS_1101 0xD0000000
90#define CS_1110 0xE0000000
91#define CS_1111 0xF0000000
92
93#define BS_0000 0x00000000
94#define BS_0001 0x01000000
95#define BS_0010 0x02000000
96#define BS_0011 0x03000000
97#define BS_0100 0x04000000
98#define BS_0101 0x05000000
99#define BS_0110 0x06000000
100#define BS_0111 0x07000000
101#define BS_1000 0x08000000
102#define BS_1001 0x09000000
103#define BS_1010 0x0A000000
104#define BS_1011 0x0B000000
105#define BS_1100 0x0C000000
106#define BS_1101 0x0D000000
107#define BS_1110 0x0E000000
108#define BS_1111 0x0F000000
109
110#define GPL0_AAAA 0x00000000
111#define GPL0_AAA0 0x00200000
112#define GPL0_AAA1 0x00300000
113#define GPL0_000A 0x00800000
114#define GPL0_0000 0x00A00000
115#define GPL0_0001 0x00B00000
116#define GPL0_111A 0x00C00000
117#define GPL0_1110 0x00E00000
118#define GPL0_1111 0x00F00000
119
120#define GPL1_0000 0x00000000
121#define GPL1_0001 0x00040000
122#define GPL1_1110 0x00080000
123#define GPL1_1111 0x000C0000
124
125#define GPL2_0000 0x00000000
126#define GPL2_0001 0x00010000
127#define GPL2_1110 0x00020000
128#define GPL2_1111 0x00030000
129
130#define GPL3_0000 0x00000000
131#define GPL3_0001 0x00004000
132#define GPL3_1110 0x00008000
133#define GPL3_1111 0x0000C000
134
135#define GPL4_0000 0x00000000
136#define GPL4_0001 0x00001000
137#define GPL4_1110 0x00002000
138#define GPL4_1111 0x00003000
139
140#define GPL5_0000 0x00000000
141#define GPL5_0001 0x00000400
142#define GPL5_1110 0x00000800
143#define GPL5_1111 0x00000C00
144#define LOOP 0x00000080
145
146#define EXEN 0x00000040
147
148#define AMX_COL 0x00000000
149#define AMX_ROW 0x00000020
150#define AMX_MAR 0x00000030
151
152#define NA 0x00000008
153
154#define UTA 0x00000004
155
156#define TODT 0x00000002
157
158#define LAST 0x00000001
159
160#define A10_AAAA GPL0_AAAA
161#define A10_AAA0 GPL0_AAA0
162#define A10_AAA1 GPL0_AAA1
163#define A10_000A GPL0_000A
164#define A10_0000 GPL0_0000
165#define A10_0001 GPL0_0001
166#define A10_111A GPL0_111A
167#define A10_1110 GPL0_1110
168#define A10_1111 GPL0_1111
169
170#define RAS_0000 GPL1_0000
171#define RAS_0001 GPL1_0001
172#define RAS_1110 GPL1_1110
173#define RAS_1111 GPL1_1111
174
175#define CAS_0000 GPL2_0000
176#define CAS_0001 GPL2_0001
177#define CAS_1110 GPL2_1110
178#define CAS_1111 GPL2_1111
179
180#define WE_0000 GPL3_0000
181#define WE_0001 GPL3_0001
182#define WE_1110 GPL3_1110
183#define WE_1111 GPL3_1111
184
185/* #define CAS_LATENCY 3 */
186#define CAS_LATENCY 2
187
188const uint sdram_table[0x40] = {
189
190#if CAS_LATENCY == 3
191 /* RSS */
192 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
193 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
194 CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
195 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
196 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
197 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
198 _NOT_USED_, _NOT_USED_,
199
200 /* RBS */
201 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
202 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
203 CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
204 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
205 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
206 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
207 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
208 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
209 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
210 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
211
212 /* WSS */
213 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
214 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
215 CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
216 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
217 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
218 _NOT_USED_, _NOT_USED_, _NOT_USED_,
219
220 /* WBS */
221 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
222 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
223 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
224 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
225 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
226 CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
227 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
228 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
229 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
230 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
231 _NOT_USED_, _NOT_USED_, _NOT_USED_,
232#endif
233
234#if CAS_LATENCY == 2
235 /* RSS */
236 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
237 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
238 CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
239 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
240 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
241 _NOT_USED_,
242 _NOT_USED_, _NOT_USED_,
243
244 /* RBS */
245 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
246 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
247 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
248 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
249 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
250 CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
251 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
252 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
253 _NOT_USED_,
254 _NOT_USED_, _NOT_USED_, _NOT_USED_,
255 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
256
257 /* WSS */
258 CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
259 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
260 CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
261 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
262 _NOT_USED_,
263 _NOT_USED_, _NOT_USED_,
264 _NOT_USED_,
265
266 /* WBS */
267 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
268 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
269 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
270 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
271 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
272 CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
273 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
274 _NOT_USED_,
275 _NOT_USED_, _NOT_USED_, _NOT_USED_,
276 _NOT_USED_, _NOT_USED_, _NOT_USED_,
277 _NOT_USED_, _NOT_USED_,
278
279#endif
280
281 /* UPT */
282 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
283 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
284 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
285 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
286 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
287 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
288 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
289 _NOT_USED_, _NOT_USED_,
290
291 /* EXC */
292 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
293 _NOT_USED_,
294
295 /* REG */
296 CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
297 CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
298};
299
300static const uint nandcs_table[0x40] = {
301 /* RSS */
302 CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
303 CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
304 CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
305 CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
306 CS_0000 | GPL4_0000 | GPL5_1111,
307 CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
308 CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
309 CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
310
311 /* RBS */
312 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
313 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
314 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
315 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
316
317 /* WSS */
318 CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
319 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
320 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
321 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
322 CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
323 CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
324 CS_0000 | GPL4_1111 | GPL5_1111,
325 CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
326
327 /* WBS */
328 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
329 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
330 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
331 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
332
333 /* UPT */
334 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
335 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
336 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
337
338 /* EXC */
339 CS_0001 | LAST,
340 _NOT_USED_,
341
342 /* REG */
343 CS_1110 ,
344 CS_0001 | LAST,
345};
346
347/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
348/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
349#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
350
351/* 9 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]352#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]353 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
354 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
355
356void check_ram(unsigned int addr, unsigned int size)
357{
358 unsigned int i, j, v, vv;
359 volatile unsigned int *p;
360 unsigned int pv;
361
362 p = (unsigned int *)addr;
363 pv = (unsigned int)p;
364 for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
365 *p++ = pv;
366
367 p = (unsigned int *)addr;
368 for (i = 0; i < size / sizeof(unsigned int); i++) {
369 v = (unsigned int)p;
370 vv = *p;
371 if (vv != v) {
372 printf("%p: read %08x instead of %08x\n", p, vv, v);
373 hang();
374 }
375 p++;
376 }
377
378 for (j = 0; j < 5; j++) {
379 switch (j) {
380 case 0: v = 0x00000000; break;
381 case 1: v = 0xffffffff; break;
382 case 2: v = 0x55555555; break;
383 case 3: v = 0xaaaaaaaa; break;
384 default:v = 0xdeadbeef; break;
385 }
386 p = (unsigned int *)addr;
387 for (i = 0; i < size / sizeof(unsigned int); i++) {
388 *p = v;
389 vv = *p;
390 if (vv != v) {
391 printf("%p: read %08x instead of %08x\n", p, vv, v);
392 hang();
393 }
394 *p = ~v;
395 p++;
396 }
397 }
398}
399
400#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0)
401
Becky Brucebd99ae72008-06-09 16:03:40 -0500[diff] [blame]402phys_size_t initdram(int board_type)
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]403{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]404 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]405 volatile memctl8xx_t *memctl = &immap->im_memctl;
406 long int size;
407 u32 d1, d2;
408
409 upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
410
411 /*
412 * Preliminary prescaler for refresh
413 */
414 memctl->memc_mptpr = MPTPR_PTP_DIV8;
415
416 memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
417
418 /*
419 * Map controller bank 3 to the SDRAM bank at preliminary address.
420 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]421 memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
422 memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]423
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]424 memctl->memc_mamr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]425
426 udelay(200);
427
428 /* perform SDRAM initialisation sequence */
429 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
430 udelay(1);
431
432 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
433 udelay(1);
434
435 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
436 udelay(1);
437
438 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
439
440 udelay(10000);
441
442
443 d1 = 0xAA55AA55;
444 *(volatile u32 *)0 = d1;
445 d2 = *(volatile u32 *)0;
446 if (d1 != d2) {
447 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
448 DO_LOOP;
449 }
450
451 d1 = 0x55AA55AA;
452 *(volatile u32 *)0 = d1;
453 d2 = *(volatile u32 *)0;
454 if (d1 != d2) {
455 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
456 DO_LOOP;
457 }
458
459 d1 = 0x12345678;
460 *(volatile u32 *)0 = d1;
461 d2 = *(volatile u32 *)0;
462 if (d1 != d2) {
463 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
464 DO_LOOP;
465 }
466
467 size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
468
469 return size;
470}
471
472/* ------------------------------------------------------------------------- */
473
474void reset_phys(void)
475{
476 int phyno;
477 unsigned short v;
478
479 udelay(10000);
480 /* reset the damn phys */
481 mii_init();
482
483 for (phyno = 0; phyno < 32; ++phyno) {
Mike Frysingerd63ee712010-12-23 15:40:12 -0500[diff] [blame]484 miiphy_read("FEC", phyno, MII_PHYSID1, &v);
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]485 if (v == 0xFFFF)
486 continue;
Mike Frysingerd63ee712010-12-23 15:40:12 -0500[diff] [blame]487 miiphy_write("FEC", phyno, MII_BMCR, BMCR_PDOWN);
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]488 udelay(10000);
Mike Frysingerd63ee712010-12-23 15:40:12 -0500[diff] [blame]489 miiphy_write("FEC", phyno, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]490 udelay(10000);
491 }
492}
493
494/* ------------------------------------------------------------------------- */
495
496/* GP = general purpose, SP = special purpose (on chip peripheral) */
497
498/* bits that can have a special purpose or can be configured as inputs/outputs */
499#define PA_GP_INMASK _BW(6)
500#define PA_GP_OUTMASK (_BW(7))
501#define PA_SP_MASK 0
502#define PA_ODR_VAL 0
503#define PA_GP_OUTVAL (_BW(7))
504#define PA_SP_DIRVAL 0
505
506#define PB_GP_INMASK 0
507#define PB_GP_OUTMASK (_B(23))
508#define PB_SP_MASK 0
509#define PB_ODR_VAL 0
510#define PB_GP_OUTVAL (_B(23))
511#define PB_SP_DIRVAL 0
512
513#define PC_GP_INMASK 0
514#define PC_GP_OUTMASK (_BW(15))
515
516#define PC_SP_MASK 0
517#define PC_SOVAL 0
518#define PC_INTVAL 0
519#define PC_GP_OUTVAL 0
520#define PC_SP_DIRVAL 0
521
522#define PE_GP_INMASK 0
523#define PE_GP_OUTMASK 0
524#define PE_GP_OUTVAL 0
525
526#define PE_SP_MASK 0
527#define PE_ODR_VAL 0
528#define PE_SP_DIRVAL 0
529
530int board_early_init_f(void)
531{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]532 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]533 volatile iop8xx_t *ioport = &immap->im_ioport;
534 volatile cpm8xx_t *cpm = &immap->im_cpm;
535 volatile memctl8xx_t *memctl = &immap->im_memctl;
536
537 (void)ioport;
538 (void)cpm;
539#if 1
540 /* NAND chip select */
541 upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
542 memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
543 memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB);
544 memctl->memc_mbmr = 0; /* all clear */
545#endif
546
547 memctl->memc_br5 &= ~BR_V;
548 memctl->memc_br6 &= ~BR_V;
549 memctl->memc_br7 &= ~BR_V;
550
551#if 1
552 ioport->iop_padat = PA_GP_OUTVAL;
553 ioport->iop_paodr = PA_ODR_VAL;
554 ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
555 ioport->iop_papar = PA_SP_MASK;
556
557 cpm->cp_pbdat = PB_GP_OUTVAL;
558 cpm->cp_pbodr = PB_ODR_VAL;
559 cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
560 cpm->cp_pbpar = PB_SP_MASK;
561
562 ioport->iop_pcdat = PC_GP_OUTVAL;
563 ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
564 ioport->iop_pcso = PC_SOVAL;
565 ioport->iop_pcint = PC_INTVAL;
566 ioport->iop_pcpar = PC_SP_MASK;
567
568 cpm->cp_pedat = PE_GP_OUTVAL;
569 cpm->cp_peodr = PE_ODR_VAL;
570 cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
571 cpm->cp_pepar = PE_SP_MASK;
572#endif
573
574 return 0;
575}
576
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]577#ifdef CONFIG_HW_WATCHDOG
578
579void hw_watchdog_reset(void)
580{
581 /* XXX add here the really funky stuff */
582}
583
584#endif
585
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]586#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
Wolfgang Denk72fdb6c2005-08-15 15:55:00 +0200[diff] [blame]587int overwrite_console(void)
588{
589 /* printf("overwrite_console called\n"); */
590 return 0;
591}
592#endif
593
594extern int drv_phone_init(void);
595extern int drv_phone_use_me(void);
596extern int drv_phone_is_idle(void);
597
598int misc_init_r(void)
599{
600 return 0;
601}
602
603int last_stage_init(void)
604{
605 reset_phys();
606
607 return 0;
608}