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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ruchika Guptaac1b2692014-10-15 11:35:30 +05302/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Kshitiz Varshneyc4686322021-09-19 17:09:53 +02004 * Copyright 2021 NXP
Ruchika Guptaac1b2692014-10-15 11:35:30 +05305 */
6
7#include <common.h>
Simon Glass63334482019-11-14 12:57:39 -07008#include <cpu_func.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Ruchika Guptaac1b2692014-10-15 11:35:30 +053010#include <malloc.h>
Breno Lima45e65122018-01-17 10:03:45 -020011#include <memalign.h>
Ruchika Guptaac1b2692014-10-15 11:35:30 +053012#include "jobdesc.h"
13#include "desc.h"
14#include "jr.h"
gaurav ranaef201592015-02-20 12:51:46 +053015#include "fsl_hash.h"
16#include <hw_sha.h>
Simon Glass274e0b02020-05-10 11:39:56 -060017#include <asm/cache.h>
Masahiro Yamada64e4f7f2016-09-21 11:28:57 +090018#include <linux/errno.h>
Ruchika Guptaac1b2692014-10-15 11:35:30 +053019
20#define CRYPTO_MAX_ALG_NAME 80
21#define SHA1_DIGEST_SIZE 20
22#define SHA256_DIGEST_SIZE 32
23
24struct caam_hash_template {
25 char name[CRYPTO_MAX_ALG_NAME];
26 unsigned int digestsize;
27 u32 alg_type;
28};
29
30enum caam_hash_algos {
31 SHA1 = 0,
32 SHA256
33};
34
35static struct caam_hash_template driver_hash[] = {
36 {
37 .name = "sha1",
38 .digestsize = SHA1_DIGEST_SIZE,
39 .alg_type = OP_ALG_ALGSEL_SHA1,
40 },
41 {
42 .name = "sha256",
43 .digestsize = SHA256_DIGEST_SIZE,
44 .alg_type = OP_ALG_ALGSEL_SHA256,
45 },
46};
47
gaurav ranaef201592015-02-20 12:51:46 +053048static enum caam_hash_algos get_hash_type(struct hash_algo *algo)
49{
50 if (!strcmp(algo->name, driver_hash[SHA1].name))
51 return SHA1;
52 else
53 return SHA256;
54}
55
56/* Create the context for progressive hashing using h/w acceleration.
57 *
58 * @ctxp: Pointer to the pointer of the context for hashing
59 * @caam_algo: Enum for SHA1 or SHA256
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +010060 * Return: 0 if ok, -ENOMEM on error
gaurav ranaef201592015-02-20 12:51:46 +053061 */
62static int caam_hash_init(void **ctxp, enum caam_hash_algos caam_algo)
63{
64 *ctxp = calloc(1, sizeof(struct sha_ctx));
65 if (*ctxp == NULL) {
66 debug("Cannot allocate memory for context\n");
67 return -ENOMEM;
68 }
69 return 0;
70}
71
72/*
73 * Update sg table for progressive hashing using h/w acceleration
74 *
75 * The context is freed by this function if an error occurs.
76 * We support at most 32 Scatter/Gather Entries.
77 *
78 * @hash_ctx: Pointer to the context for hashing
79 * @buf: Pointer to the buffer being hashed
80 * @size: Size of the buffer being hashed
81 * @is_last: 1 if this is the last update; 0 otherwise
82 * @caam_algo: Enum for SHA1 or SHA256
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +010083 * Return: 0 if ok, -EINVAL on error
gaurav ranaef201592015-02-20 12:51:46 +053084 */
85static int caam_hash_update(void *hash_ctx, const void *buf,
86 unsigned int size, int is_last,
87 enum caam_hash_algos caam_algo)
88{
Heinrich Schuchardt0dd1d842020-06-27 10:13:55 +020089 uint32_t final;
Ye Li3c3e9a12021-03-25 17:30:36 +080090 caam_dma_addr_t addr = virt_to_phys((void *)buf);
gaurav ranaef201592015-02-20 12:51:46 +053091 struct sha_ctx *ctx = hash_ctx;
92
93 if (ctx->sg_num >= MAX_SG_32) {
94 free(ctx);
95 return -EINVAL;
96 }
97
Ye Li3c3e9a12021-03-25 17:30:36 +080098#ifdef CONFIG_CAAM_64BIT
Aneesh Bansal43421822015-10-29 22:58:03 +053099 sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32));
gaurav ranaef201592015-02-20 12:51:46 +0530100#else
Aneesh Bansal43421822015-10-29 22:58:03 +0530101 sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0);
gaurav ranaef201592015-02-20 12:51:46 +0530102#endif
Ye Li3c3e9a12021-03-25 17:30:36 +0800103 sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_lo, (caam_dma_addr_t)addr);
gaurav ranaef201592015-02-20 12:51:46 +0530104
105 sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag,
106 (size & SG_ENTRY_LENGTH_MASK));
107
108 ctx->sg_num++;
109
110 if (is_last) {
111 final = sec_in32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag) |
112 SG_ENTRY_FINAL_BIT;
113 sec_out32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag, final);
114 }
115
116 return 0;
117}
118
119/*
120 * Perform progressive hashing on the given buffer and copy hash at
121 * destination buffer
122 *
Kshitiz Varshneyc4686322021-09-19 17:09:53 +0200123 * The context is freed after successful completion of hash operation.
124 * In case of failure, context is not freed.
gaurav ranaef201592015-02-20 12:51:46 +0530125 * @hash_ctx: Pointer to the context for hashing
126 * @dest_buf: Pointer to the destination buffer where hash is to be copied
127 * @size: Size of the buffer being hashed
128 * @caam_algo: Enum for SHA1 or SHA256
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100129 * Return: 0 if ok, -EINVAL on error
gaurav ranaef201592015-02-20 12:51:46 +0530130 */
131static int caam_hash_finish(void *hash_ctx, void *dest_buf,
132 int size, enum caam_hash_algos caam_algo)
133{
134 uint32_t len = 0;
135 struct sha_ctx *ctx = hash_ctx;
136 int i = 0, ret = 0;
137
138 if (size < driver_hash[caam_algo].digestsize) {
gaurav ranaef201592015-02-20 12:51:46 +0530139 return -EINVAL;
140 }
141
142 for (i = 0; i < ctx->sg_num; i++)
143 len += (sec_in32(&ctx->sg_tbl[i].len_flag) &
144 SG_ENTRY_LENGTH_MASK);
145
146 inline_cnstr_jobdesc_hash(ctx->sha_desc, (uint8_t *)ctx->sg_tbl, len,
147 ctx->hash,
148 driver_hash[caam_algo].alg_type,
149 driver_hash[caam_algo].digestsize,
150 1);
151
Gaurav Jain5c2c4062022-05-11 14:23:19 +0530152 flush_dcache_range((ulong)ctx->sg_tbl, (ulong)(ctx->sg_tbl) + len);
153 flush_dcache_range((ulong)ctx->sha_desc,
154 (ulong)(ctx->sha_desc) + (sizeof(uint32_t) * MAX_CAAM_DESCSIZE));
155 flush_dcache_range((ulong)ctx->hash,
156 (ulong)(ctx->hash) + driver_hash[caam_algo].digestsize);
157
gaurav ranaef201592015-02-20 12:51:46 +0530158 ret = run_descriptor_jr(ctx->sha_desc);
159
Kshitiz Varshneyc4686322021-09-19 17:09:53 +0200160 if (ret) {
gaurav ranaef201592015-02-20 12:51:46 +0530161 debug("Error %x\n", ret);
Kshitiz Varshneyc4686322021-09-19 17:09:53 +0200162 return ret;
163 } else {
Gaurav Jain5c2c4062022-05-11 14:23:19 +0530164 invalidate_dcache_range((ulong)ctx->hash,
165 (ulong)(ctx->hash) + driver_hash[caam_algo].digestsize);
gaurav ranaef201592015-02-20 12:51:46 +0530166 memcpy(dest_buf, ctx->hash, sizeof(ctx->hash));
Kshitiz Varshneyc4686322021-09-19 17:09:53 +0200167 }
gaurav ranaef201592015-02-20 12:51:46 +0530168 free(ctx);
169 return ret;
170}
171
Ruchika Guptaac1b2692014-10-15 11:35:30 +0530172int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
173 unsigned char *pout, enum caam_hash_algos algo)
174{
175 int ret = 0;
176 uint32_t *desc;
Breno Lima45e65122018-01-17 10:03:45 -0200177 unsigned int size;
Ruchika Guptaac1b2692014-10-15 11:35:30 +0530178
Gaurav Jain95fa7942022-04-19 10:52:28 +0530179 desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
180 if (!desc) {
181 debug("Not enough memory for descriptor allocation\n");
182 return -ENOMEM;
183 }
184
Breno Lima45e65122018-01-17 10:03:45 -0200185 size = ALIGN(buf_len, ARCH_DMA_MINALIGN);
186 flush_dcache_range((unsigned long)pbuf, (unsigned long)pbuf + size);
187
Ruchika Guptaac1b2692014-10-15 11:35:30 +0530188 inline_cnstr_jobdesc_hash(desc, pbuf, buf_len, pout,
189 driver_hash[algo].alg_type,
190 driver_hash[algo].digestsize,
191 0);
192
Breno Lima45e65122018-01-17 10:03:45 -0200193 size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN);
194 flush_dcache_range((unsigned long)desc, (unsigned long)desc + size);
Gaurav Jain95fa7942022-04-19 10:52:28 +0530195 size = ALIGN(driver_hash[algo].digestsize, ARCH_DMA_MINALIGN);
196 invalidate_dcache_range((unsigned long)pout, (unsigned long)pout + size);
Breno Lima45e65122018-01-17 10:03:45 -0200197
Ruchika Guptaac1b2692014-10-15 11:35:30 +0530198 ret = run_descriptor_jr(desc);
199
Breno Lima45e65122018-01-17 10:03:45 -0200200 size = ALIGN(driver_hash[algo].digestsize, ARCH_DMA_MINALIGN);
201 invalidate_dcache_range((unsigned long)pout,
202 (unsigned long)pout + size);
203
Ruchika Guptaac1b2692014-10-15 11:35:30 +0530204 free(desc);
205 return ret;
206}
207
208void hw_sha256(const unsigned char *pbuf, unsigned int buf_len,
209 unsigned char *pout, unsigned int chunk_size)
210{
211 if (caam_hash(pbuf, buf_len, pout, SHA256))
212 printf("CAAM was not setup properly or it is faulty\n");
213}
214
215void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
216 unsigned char *pout, unsigned int chunk_size)
217{
218 if (caam_hash(pbuf, buf_len, pout, SHA1))
219 printf("CAAM was not setup properly or it is faulty\n");
220}
gaurav ranaef201592015-02-20 12:51:46 +0530221
222int hw_sha_init(struct hash_algo *algo, void **ctxp)
223{
224 return caam_hash_init(ctxp, get_hash_type(algo));
225}
226
227int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf,
228 unsigned int size, int is_last)
229{
230 return caam_hash_update(ctx, buf, size, is_last, get_hash_type(algo));
231}
232
233int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf,
234 int size)
235{
236 return caam_hash_finish(ctx, dest_buf, size, get_hash_type(algo));
237}