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Tom Rini8b0c8a12018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +01002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +01004 */
5
6#include <common.h>
7#include <dm.h>
8#include <asm/io.h>
9#include <asm/arch/ddr.h>
10#include <power/pmic.h>
Patrick Delaunay91be5942019-02-04 11:26:16 +010011#include <power/stpmic1.h>
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +010012
Patrick Delaunay82168e82018-05-17 14:50:46 +020013#ifdef CONFIG_DEBUG_UART_BOARD_INIT
14void board_debug_uart_init(void)
15{
16#if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE)
17
18#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
19#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
20
21 /* UART4 clock enable */
22 setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
23
24#define GPIOG_BASE 0x50008000
25 /* GPIOG clock enable */
26 writel(BIT(6), RCC_MP_AHB4ENSETR);
27 /* GPIO configuration for EVAL board
28 * => Uart4 TX = G11
29 */
30 writel(0xffbfffff, GPIOG_BASE + 0x00);
31 writel(0x00006000, GPIOG_BASE + 0x24);
32#else
33
34#error("CONFIG_DEBUG_UART_BASE: not supported value")
35
36#endif
37}
38#endif
39
Patrick Delaunayd79218f2019-02-04 11:26:17 +010040#ifdef CONFIG_PMIC_STPMIC1
Patrick Delaunay4175f452019-04-10 14:09:26 +020041int board_ddr_power_init(enum ddr_type ddr_type)
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +010042{
43 struct udevice *dev;
Patrick Delaunay4175f452019-04-10 14:09:26 +020044 bool buck3_at_1800000v = false;
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +010045 int ret;
Patrick Delaunay2ebc2112020-03-06 11:14:03 +010046 u32 buck2;
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +010047
48 ret = uclass_get_device_by_driver(UCLASS_PMIC,
Patrick Delaunayd79218f2019-02-04 11:26:17 +010049 DM_GET_DRIVER(pmic_stpmic1), &dev);
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +010050 if (ret)
51 /* No PMIC on board */
52 return 0;
53
Patrick Delaunay4175f452019-04-10 14:09:26 +020054 switch (ddr_type) {
55 case STM32MP_DDR3:
56 /* VTT = Set LDO3 to sync mode */
57 ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
58 if (ret < 0)
59 return ret;
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +010060
Patrick Delaunay4175f452019-04-10 14:09:26 +020061 ret &= ~STPMIC1_LDO3_MODE;
62 ret &= ~STPMIC1_LDO12356_VOUT_MASK;
63 ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +010064
Patrick Delaunay4175f452019-04-10 14:09:26 +020065 ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
66 ret);
67 if (ret < 0)
68 return ret;
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +010069
Patrick Delaunay4175f452019-04-10 14:09:26 +020070 /* VDD_DDR = Set BUCK2 to 1.35V */
71 ret = pmic_clrsetbits(dev,
72 STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
73 STPMIC1_BUCK_VOUT_MASK,
74 STPMIC1_BUCK2_1350000V);
75 if (ret < 0)
76 return ret;
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +010077
Patrick Delaunay4175f452019-04-10 14:09:26 +020078 /* Enable VDD_DDR = BUCK2 */
79 ret = pmic_clrsetbits(dev,
80 STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
81 STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
82 if (ret < 0)
83 return ret;
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +010084
Patrick Delaunay4175f452019-04-10 14:09:26 +020085 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +010086
Patrick Delaunay4175f452019-04-10 14:09:26 +020087 /* Enable VREF */
88 ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
89 STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
90 if (ret < 0)
91 return ret;
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +010092
Patrick Delaunay4175f452019-04-10 14:09:26 +020093 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +010094
Patrick Delaunay4175f452019-04-10 14:09:26 +020095 /* Enable VTT = LDO3 */
96 ret = pmic_clrsetbits(dev,
97 STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
98 STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
99 if (ret < 0)
100 return ret;
101
102 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
103
104 break;
105
Patrick Delaunay2ebc2112020-03-06 11:14:03 +0100106 case STM32MP_LPDDR2_16:
107 case STM32MP_LPDDR2_32:
108 case STM32MP_LPDDR3_16:
109 case STM32MP_LPDDR3_32:
Patrick Delaunay4175f452019-04-10 14:09:26 +0200110 /*
111 * configure VDD_DDR1 = LDO3
112 * Set LDO3 to 1.8V
113 * + bypass mode if BUCK3 = 1.8V
114 * + normal mode if BUCK3 != 1.8V
115 */
116 ret = pmic_reg_read(dev,
117 STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
118 if (ret < 0)
119 return ret;
120
121 if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
122 buck3_at_1800000v = true;
123
124 ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
125 if (ret < 0)
126 return ret;
127
128 ret &= ~STPMIC1_LDO3_MODE;
129 ret &= ~STPMIC1_LDO12356_VOUT_MASK;
130 ret |= STPMIC1_LDO3_1800000;
131 if (buck3_at_1800000v)
132 ret |= STPMIC1_LDO3_MODE;
133
134 ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
135 ret);
136 if (ret < 0)
137 return ret;
138
Patrick Delaunay2ebc2112020-03-06 11:14:03 +0100139 /* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
140 switch (ddr_type) {
141 case STM32MP_LPDDR2_32:
142 case STM32MP_LPDDR3_32:
143 buck2 = STPMIC1_BUCK2_1250000V;
144 break;
145 default:
146 case STM32MP_LPDDR2_16:
147 case STM32MP_LPDDR3_16:
148 buck2 = STPMIC1_BUCK2_1200000V;
149 break;
150 }
151
Patrick Delaunay4175f452019-04-10 14:09:26 +0200152 ret = pmic_clrsetbits(dev,
153 STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
154 STPMIC1_BUCK_VOUT_MASK,
Patrick Delaunay2ebc2112020-03-06 11:14:03 +0100155 buck2);
Patrick Delaunay4175f452019-04-10 14:09:26 +0200156 if (ret < 0)
157 return ret;
158
159 /* Enable VDD_DDR1 = LDO3 */
160 ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
161 STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
162 if (ret < 0)
163 return ret;
164
165 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
166
167 /* Enable VDD_DDR2 =BUCK2 */
168 ret = pmic_clrsetbits(dev,
169 STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
170 STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
171 if (ret < 0)
172 return ret;
173
174 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
175
176 /* Enable VREF */
177 ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
178 STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
179 if (ret < 0)
180 return ret;
181
182 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
183
184 break;
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +0100185
Patrick Delaunay4175f452019-04-10 14:09:26 +0200186 default:
187 break;
188 };
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +0100189
190 return 0;
191}
192#endif