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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jon Masond59b5862017-03-17 12:12:14 -04002/*
3 * (C) Copyright 2016 Broadcom Ltd.
Jon Masond59b5862017-03-17 12:12:14 -04004 */
5#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -07006#include <cpu_func.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -07007#include <init.h>
Jon Masond59b5862017-03-17 12:12:14 -04008#include <asm/system.h>
9#include <asm/armv8/mmu.h>
10
11static struct mm_region ns2_mem_map[] = {
12 {
13 .virt = 0x0UL,
14 .phys = 0x0UL,
15 .size = 0x80000000UL,
16 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
17 PTE_BLOCK_NON_SHARE |
18 PTE_BLOCK_PXN | PTE_BLOCK_UXN
19 }, {
20 .virt = 0x80000000UL,
21 .phys = 0x80000000UL,
22 .size = 0xff80000000UL,
23 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
24 PTE_BLOCK_INNER_SHARE
25 }, {
26 /* List terminator */
27 0,
28 }
29};
30
31struct mm_region *mem_map = ns2_mem_map;
32
33DECLARE_GLOBAL_DATA_PTR;
34
35int board_init(void)
36{
37 return 0;
38}
39
40int dram_init(void)
41{
42 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
43 PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE);
44 return 0;
45}
46
Simon Glass2f949c32017-03-31 08:40:32 -060047int dram_init_banksize(void)
Jon Masond59b5862017-03-17 12:12:14 -040048{
49 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
50 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
51
52 gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE;
53 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
Simon Glass2f949c32017-03-31 08:40:32 -060054
55 return 0;
Jon Masond59b5862017-03-17 12:12:14 -040056}
57
58void reset_cpu(ulong addr)
59{
60 psci_system_reset();
61}