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git01.mediatek.com / filogic / uboot / 74cd30ad163ab097fbdcd1419eb8d29370a17be9 / . / arch / arm / mach-meson / board-axg.c
blob: 6874458e36ac7d02fc0861fde2d49c21a1abc5ab [file] [log] [blame]
Neil Armstrong0fca9232018-09-05 15:56:12 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7#include <common.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -0700[diff] [blame]8#include <init.h>
Neil Armstrong2fbfcbb2018-07-27 14:10:00 +0200[diff] [blame]9#include <asm/arch/boot.h>
Neil Armstrong0fca9232018-09-05 15:56:12 +0200[diff] [blame]10#include <asm/arch/eth.h>
11#include <asm/arch/axg.h>
12#include <asm/arch/mem.h>
13#include <asm/io.h>
14#include <asm/armv8/mmu.h>
15#include <linux/sizes.h>
16#include <phy.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
Neil Armstrong2fbfcbb2018-07-27 14:10:00 +0200[diff] [blame]20int meson_get_boot_device(void)
21{
22 return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
23}
24
Neil Armstrong0fca9232018-09-05 15:56:12 +0200[diff] [blame]25/* Configure the reserved memory zones exported by the secure registers
26 * into EFI and DTB reserved memory entries.
27 */
28void meson_init_reserved_memory(void *fdt)
29{
30 u64 bl31_size, bl31_start;
31 u64 bl32_size, bl32_start;
32 u32 reg;
33
34 /*
35 * Get ARM Trusted Firmware reserved memory zones in :
36 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
37 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
38 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
39 */
40 reg = readl(AXG_AO_SEC_GP_CFG3);
41
42 bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
43 >> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
44 bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
45
46 bl31_start = readl(AXG_AO_SEC_GP_CFG5);
47 bl32_start = readl(AXG_AO_SEC_GP_CFG4);
48
49 /* Add BL31 reserved zone */
50 if (bl31_start && bl31_size)
51 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
52
53 /* Add BL32 reserved zone */
54 if (bl32_start && bl32_size)
55 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
56}
57
58phys_size_t get_effective_memsize(void)
59{
60 /* Size is reported in MiB, convert it in bytes */
61 return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
62 >> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
63}
64
65static struct mm_region axg_mem_map[] = {
66 {
67 .virt = 0x0UL,
68 .phys = 0x0UL,
69 .size = 0x80000000UL,
70 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
71 PTE_BLOCK_INNER_SHARE
72 }, {
73 .virt = 0xf0000000UL,
74 .phys = 0xf0000000UL,
75 .size = 0x10000000UL,
76 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
77 PTE_BLOCK_NON_SHARE |
78 PTE_BLOCK_PXN | PTE_BLOCK_UXN
79 }, {
80 /* List terminator */
81 0,
82 }
83};
84
85struct mm_region *mem_map = axg_mem_map;
86
87/* Configure the Ethernet MAC with the requested interface mode
88 * with some optional flags.
89 */
90void meson_eth_init(phy_interface_t mode, unsigned int flags)
91{
92 switch (mode) {
93 case PHY_INTERFACE_MODE_RGMII:
94 case PHY_INTERFACE_MODE_RGMII_ID:
95 case PHY_INTERFACE_MODE_RGMII_RXID:
96 case PHY_INTERFACE_MODE_RGMII_TXID:
97 /* Set RGMII mode */
98 setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
99 AXG_ETH_REG_0_TX_PHASE(1) |
100 AXG_ETH_REG_0_TX_RATIO(4) |
101 AXG_ETH_REG_0_PHY_CLK_EN |
102 AXG_ETH_REG_0_CLK_EN);
103 break;
104
105 case PHY_INTERFACE_MODE_RMII:
106 /* Set RMII mode */
107 out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
108 AXG_ETH_REG_0_INVERT_RMII_CLK |
109 AXG_ETH_REG_0_CLK_EN);
110 break;
111
112 default:
113 printf("Invalid Ethernet interface mode\n");
114 return;
115 }
116
117 /* Enable power gate */
118 clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
119}