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git01.mediatek.com / filogic / uboot / 74ae33286d041513005e53455affceacf4582bd5 / . / board / xilinx / common / fru.h
blob: 586c41b66ef78dff994818efba6249a1de978e0b [file] [log] [blame]
Siva Durga Prasad Paladugu7177d022019-04-10 12:38:10 +0530[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2019 Xilinx, Inc.
4 * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
5 */
6
7#ifndef __FRU_H
8#define __FRU_H
Ashok Reddy Soma9f60e442022-02-23 15:00:59 +0100[diff] [blame]9#include <net.h>
Siva Durga Prasad Paladugu7177d022019-04-10 12:38:10 +0530[diff] [blame]10
11struct fru_common_hdr {
12 u8 version;
13 u8 off_internal;
14 u8 off_chassis;
15 u8 off_board;
16 u8 off_product;
17 u8 off_multirec;
18 u8 pad;
19 u8 crc;
20};
21
22#define FRU_BOARD_MAX_LEN 32
Ashok Reddy Soma9f60e442022-02-23 15:00:59 +0100[diff] [blame]23#define FRU_MAX_NO_OF_MAC_ADDR 4
Siva Durga Prasad Paladugu7177d022019-04-10 12:38:10 +0530[diff] [blame]24
Michal Simekd5c33212019-04-15 13:54:09 +0200[diff] [blame]25struct __packed fru_board_info_header {
26 u8 ver;
27 u8 len;
28 u8 lang_code;
29 u8 time[3];
30};
31
32struct __packed fru_board_info_member {
33 u8 type_len;
34 u8 *name;
35};
36
Siva Durga Prasad Paladugu7177d022019-04-10 12:38:10 +0530[diff] [blame]37struct fru_board_data {
38 u8 ver;
39 u8 len;
40 u8 lang_code;
41 u8 time[3];
42 u8 manufacturer_type_len;
43 u8 manufacturer_name[FRU_BOARD_MAX_LEN];
44 u8 product_name_type_len;
45 u8 product_name[FRU_BOARD_MAX_LEN];
46 u8 serial_number_type_len;
47 u8 serial_number[FRU_BOARD_MAX_LEN];
48 u8 part_number_type_len;
49 u8 part_number[FRU_BOARD_MAX_LEN];
50 u8 file_id_type_len;
51 u8 file_id[FRU_BOARD_MAX_LEN];
Michal Simekd5c33212019-04-15 13:54:09 +0200[diff] [blame]52 /* Xilinx custom fields */
53 u8 rev_type_len;
54 u8 rev[FRU_BOARD_MAX_LEN];
Michal Simek2fc78122020-11-06 13:58:01 +0100[diff] [blame]55 u8 pcie_type_len;
56 u8 pcie[FRU_BOARD_MAX_LEN];
57 u8 uuid_type_len;
58 u8 uuid[FRU_BOARD_MAX_LEN];
Siva Durga Prasad Paladugu7177d022019-04-10 12:38:10 +0530[diff] [blame]59};
60
Ashok Reddy Soma9f60e442022-02-23 15:00:59 +0100[diff] [blame]61struct fru_multirec_hdr {
62 u8 rec_type;
63 u8 type;
64 u8 len;
65 u8 csum;
66 u8 hdr_csum;
67};
68
69struct fru_multirec_mac {
70 u8 xlnx_iana_id[3];
71 u8 ver;
72 u8 macid[FRU_MAX_NO_OF_MAC_ADDR][ETH_ALEN];
73};
74
Siva Durga Prasad Paladugu7177d022019-04-10 12:38:10 +0530[diff] [blame]75struct fru_table {
Siva Durga Prasad Paladugu7177d022019-04-10 12:38:10 +0530[diff] [blame]76 struct fru_common_hdr hdr;
77 struct fru_board_data brd;
Ashok Reddy Soma9f60e442022-02-23 15:00:59 +0100[diff] [blame]78 struct fru_multirec_mac mac;
Michal Simekb682f002020-11-06 13:53:01 +0100[diff] [blame]79 bool captured;
Siva Durga Prasad Paladugu7177d022019-04-10 12:38:10 +0530[diff] [blame]80};
81
82#define FRU_TYPELEN_CODE_MASK 0xC0
83#define FRU_TYPELEN_LEN_MASK 0x3F
84#define FRU_COMMON_HDR_VER_MASK 0xF
85#define FRU_COMMON_HDR_LEN_MULTIPLIER 8
86#define FRU_LANG_CODE_ENGLISH 0
87#define FRU_LANG_CODE_ENGLISH_1 25
88#define FRU_TYPELEN_EOF 0xC1
Ashok Reddy Soma9f60e442022-02-23 15:00:59 +0100[diff] [blame]89#define FRU_MULTIREC_TYPE_OEM 0xD2
90#define FRU_MULTIREC_MAC_OFFSET 4
91#define FRU_LAST_REC BIT(7)
92#define FRU_DUT_MACID 0x31
Michal Simek292b9ae2022-11-23 12:48:44 +0100[diff] [blame]93#define FRU_SC_MACID 0x11
Siva Durga Prasad Paladugu7177d022019-04-10 12:38:10 +0530[diff] [blame]94
95/* This should be minimum of fields */
96#define FRU_BOARD_AREA_TOTAL_FIELDS 5
97#define FRU_TYPELEN_TYPE_SHIFT 6
98#define FRU_TYPELEN_TYPE_BINARY 0
99#define FRU_TYPELEN_TYPE_ASCII8 3
100
101int fru_display(int verbose);
102int fru_capture(unsigned long addr);
Michal Simekd5c33212019-04-15 13:54:09 +0200[diff] [blame]103int fru_generate(unsigned long addr, char *manufacturer, char *board_name,
104 char *serial_no, char *part_no, char *revision);
Siva Durga Prasad Paladugu7177d022019-04-10 12:38:10 +0530[diff] [blame]105u8 fru_checksum(u8 *addr, u8 len);
106
107extern struct fru_table fru_data;
108
109#endif /* FRU_H */