Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Vitaly Andrianov | bbf8ac2 | 2015-09-19 16:26:43 +0530 | [diff] [blame] | 2 | /* |
| 3 | * K2G: DDR3 initialization |
| 4 | * |
| 5 | * (C) Copyright 2015 |
| 6 | * Texas Instruments Incorporated, <www.ti.com> |
Vitaly Andrianov | bbf8ac2 | 2015-09-19 16:26:43 +0530 | [diff] [blame] | 7 | */ |
| 8 | |
Vitaly Andrianov | bbf8ac2 | 2015-09-19 16:26:43 +0530 | [diff] [blame] | 9 | #include "ddr3_cfg.h" |
| 10 | #include <asm/arch/ddr3.h> |
Rex Chang | 4df43d4 | 2017-12-28 20:39:59 +0530 | [diff] [blame] | 11 | #include <asm/arch/hardware.h> |
Cooper Jr., Franklin | 2b0273a | 2017-06-16 17:25:24 -0500 | [diff] [blame] | 12 | #include "board.h" |
Vitaly Andrianov | bbf8ac2 | 2015-09-19 16:26:43 +0530 | [diff] [blame] | 13 | |
Cooper Jr., Franklin | 2b0273a | 2017-06-16 17:25:24 -0500 | [diff] [blame] | 14 | /* K2G GP EVM DDR3 Configuration */ |
Lokesh Vutla | ea3dae4 | 2017-12-28 20:40:03 +0530 | [diff] [blame] | 15 | static struct ddr3_phy_config ddr3phy_800_2g = { |
Vitaly Andrianov | bbf8ac2 | 2015-09-19 16:26:43 +0530 | [diff] [blame] | 16 | .pllcr = 0x000DC000ul, |
| 17 | .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), |
| 18 | .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), |
| 19 | .ptr0 = 0x42C21590ul, |
| 20 | .ptr1 = 0xD05612C0ul, |
| 21 | .ptr2 = 0, |
| 22 | .ptr3 = 0x06C30D40ul, |
| 23 | .ptr4 = 0x06413880ul, |
| 24 | .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), |
| 25 | .dcr_val = ((1 << 10)), |
| 26 | .dtpr0 = 0x550F6644ul, |
| 27 | .dtpr1 = 0x328341E0ul, |
| 28 | .dtpr2 = 0x50022A00ul, |
| 29 | .mr0 = 0x00001430ul, |
| 30 | .mr1 = 0x00000006ul, |
Cooper Jr., Franklin | 2247db6 | 2017-06-16 17:25:20 -0500 | [diff] [blame] | 31 | .mr2 = 0x00000000ul, |
Vitaly Andrianov | bbf8ac2 | 2015-09-19 16:26:43 +0530 | [diff] [blame] | 32 | .dtcr = 0x710035C7ul, |
| 33 | .pgcr2 = 0x00F03D09ul, |
| 34 | .zq0cr1 = 0x0001005Dul, |
| 35 | .zq1cr1 = 0x0001005Bul, |
| 36 | .zq2cr1 = 0x0001005Bul, |
| 37 | .pir_v1 = 0x00000033ul, |
Cooper Jr., Franklin | 87b4b20 | 2017-06-16 17:25:21 -0500 | [diff] [blame] | 38 | .datx8_2_mask = 0, |
| 39 | .datx8_2_val = 0, |
| 40 | .datx8_3_mask = 0, |
| 41 | .datx8_3_val = 0, |
| 42 | .datx8_4_mask = 0, |
| 43 | .datx8_4_val = ((1 << 0)), |
| 44 | .datx8_5_mask = DXEN_MASK, |
| 45 | .datx8_5_val = 0, |
| 46 | .datx8_6_mask = DXEN_MASK, |
| 47 | .datx8_6_val = 0, |
| 48 | .datx8_7_mask = DXEN_MASK, |
| 49 | .datx8_7_val = 0, |
| 50 | .datx8_8_mask = DXEN_MASK, |
| 51 | .datx8_8_val = 0, |
Vitaly Andrianov | bbf8ac2 | 2015-09-19 16:26:43 +0530 | [diff] [blame] | 52 | .pir_v2 = 0x00000F81ul, |
| 53 | }; |
| 54 | |
Rex Chang | 4df43d4 | 2017-12-28 20:39:59 +0530 | [diff] [blame] | 55 | static struct ddr3_phy_config ddr3phy_1066_2g = { |
| 56 | .pllcr = 0x000DC000ul, |
| 57 | .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), |
| 58 | .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)), |
| 59 | .ptr0 = 0x42C21590ul, |
| 60 | .ptr1 = 0xD05612C0ul, |
| 61 | .ptr2 = 0, |
| 62 | .ptr3 = 0x0904111Dul, |
| 63 | .ptr4 = 0x0859A072ul, |
| 64 | .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), |
| 65 | .dcr_val = ((1 << 10)), |
| 66 | .dtpr0 = 0x6D147744ul, |
| 67 | .dtpr1 = 0x32845A80ul, |
| 68 | .dtpr2 = 0x50023600ul, |
| 69 | .mr0 = 0x00001830ul, |
| 70 | .mr1 = 0x00000006ul, |
| 71 | .mr2 = 0x00000000ul, |
| 72 | .dtcr = 0x710035C7ul, |
| 73 | .pgcr2 = 0x00F05159ul, |
| 74 | .zq0cr1 = 0x0001005Dul, |
| 75 | .zq1cr1 = 0x0001005Bul, |
| 76 | .zq2cr1 = 0x0001005Bul, |
| 77 | .pir_v1 = 0x00000033ul, |
| 78 | .datx8_2_mask = 0, |
| 79 | .datx8_2_val = 0, |
| 80 | .datx8_3_mask = 0, |
| 81 | .datx8_3_val = 0, |
| 82 | .datx8_4_mask = 0, |
| 83 | .datx8_4_val = ((1 << 0)), |
| 84 | .datx8_5_mask = DXEN_MASK, |
| 85 | .datx8_5_val = 0, |
| 86 | .datx8_6_mask = DXEN_MASK, |
| 87 | .datx8_6_val = 0, |
| 88 | .datx8_7_mask = DXEN_MASK, |
| 89 | .datx8_7_val = 0, |
| 90 | .datx8_8_mask = DXEN_MASK, |
| 91 | .datx8_8_val = 0, |
| 92 | .pir_v2 = 0x00000F81ul, |
| 93 | }; |
| 94 | |
Lokesh Vutla | ea3dae4 | 2017-12-28 20:40:03 +0530 | [diff] [blame] | 95 | static struct ddr3_emif_config ddr3_800_2g = { |
Vitaly Andrianov | bbf8ac2 | 2015-09-19 16:26:43 +0530 | [diff] [blame] | 96 | .sdcfg = 0x62005662ul, |
| 97 | .sdtim1 = 0x0A385033ul, |
| 98 | .sdtim2 = 0x00001CA5ul, |
| 99 | .sdtim3 = 0x21ADFF32ul, |
| 100 | .sdtim4 = 0x533F067Ful, |
| 101 | .zqcfg = 0x70073200ul, |
| 102 | .sdrfc = 0x00000C34ul, |
| 103 | }; |
| 104 | |
Lokesh Vutla | ea3dae4 | 2017-12-28 20:40:03 +0530 | [diff] [blame] | 105 | static struct ddr3_emif_config ddr3_1066_2g = { |
Rex Chang | 4df43d4 | 2017-12-28 20:39:59 +0530 | [diff] [blame] | 106 | .sdcfg = 0x62005662ul, |
| 107 | .sdtim1 = 0x0E4C6843ul, |
| 108 | .sdtim2 = 0x00001CC6ul, |
| 109 | .sdtim3 = 0x323DFF32ul, |
| 110 | .sdtim4 = 0x533F08AFul, |
| 111 | .zqcfg = 0x70073200ul, |
| 112 | .sdrfc = 0x00001044ul, |
| 113 | }; |
| 114 | |
Cooper Jr., Franklin | 2b0273a | 2017-06-16 17:25:24 -0500 | [diff] [blame] | 115 | /* K2G ICE evm DDR3 Configuration */ |
Lokesh Vutla | ea3dae4 | 2017-12-28 20:40:03 +0530 | [diff] [blame] | 116 | static struct ddr3_phy_config ddr3phy_800_512mb = { |
Cooper Jr., Franklin | 2b0273a | 2017-06-16 17:25:24 -0500 | [diff] [blame] | 117 | .pllcr = 0x000DC000ul, |
| 118 | .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), |
| 119 | .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)), |
| 120 | .ptr0 = 0x42C21590ul, |
| 121 | .ptr1 = 0xD05612C0ul, |
| 122 | .ptr2 = 0, |
| 123 | .ptr3 = 0x06C30D40ul, |
| 124 | .ptr4 = 0x06413880ul, |
| 125 | .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), |
| 126 | .dcr_val = ((1 << 10)), |
| 127 | .dtpr0 = 0x550E6644ul, |
| 128 | .dtpr1 = 0x32834200ul, |
| 129 | .dtpr2 = 0x50022A00ul, |
| 130 | .mr0 = 0x00001430ul, |
| 131 | .mr1 = 0x00000006ul, |
| 132 | .mr2 = 0x00000008ul, |
| 133 | .dtcr = 0x710035C7ul, |
| 134 | .pgcr2 = 0x00F03D09ul, |
| 135 | .zq0cr1 = 0x0001005Dul, |
| 136 | .zq1cr1 = 0x0001005Bul, |
| 137 | .zq2cr1 = 0x0001005Bul, |
| 138 | .pir_v1 = 0x00000033ul, |
| 139 | .datx8_2_mask = DXEN_MASK, |
| 140 | .datx8_2_val = 0, |
| 141 | .datx8_3_mask = DXEN_MASK, |
| 142 | .datx8_3_val = 0, |
| 143 | .datx8_4_mask = DXEN_MASK, |
| 144 | .datx8_4_val = 0, |
| 145 | .datx8_5_mask = DXEN_MASK, |
| 146 | .datx8_5_val = 0, |
| 147 | .datx8_6_mask = DXEN_MASK, |
| 148 | .datx8_6_val = 0, |
| 149 | .datx8_7_mask = DXEN_MASK, |
| 150 | .datx8_7_val = 0, |
| 151 | .datx8_8_mask = DXEN_MASK, |
| 152 | .datx8_8_val = 0, |
| 153 | .pir_v2 = 0x00000F81ul, |
| 154 | }; |
| 155 | |
Lokesh Vutla | ea3dae4 | 2017-12-28 20:40:03 +0530 | [diff] [blame] | 156 | static struct ddr3_emif_config ddr3_800_512mb = { |
Cooper Jr., Franklin | 2b0273a | 2017-06-16 17:25:24 -0500 | [diff] [blame] | 157 | .sdcfg = 0x62006662ul, |
| 158 | .sdtim1 = 0x0A385033ul, |
| 159 | .sdtim2 = 0x00001CA5ul, |
| 160 | .sdtim3 = 0x21ADFF32ul, |
| 161 | .sdtim4 = 0x533F067Ful, |
| 162 | .zqcfg = 0x70073200ul, |
| 163 | .sdrfc = 0x00000C34ul, |
| 164 | }; |
| 165 | |
Vitaly Andrianov | bbf8ac2 | 2015-09-19 16:26:43 +0530 | [diff] [blame] | 166 | u32 ddr3_init(void) |
| 167 | { |
| 168 | /* Reset DDR3 PHY after PLL enabled */ |
| 169 | ddr3_reset_ddrphy(); |
Rex Chang | 4df43d4 | 2017-12-28 20:39:59 +0530 | [diff] [blame] | 170 | if (board_is_k2g_g1()) { |
| 171 | ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1066_2g); |
| 172 | ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1066_2g); |
| 173 | } else if (board_is_k2g_gp()) { |
Cooper Jr., Franklin | 2b0273a | 2017-06-16 17:25:24 -0500 | [diff] [blame] | 174 | ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g); |
| 175 | ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g); |
Lokesh Vutla | ac38c92 | 2020-12-17 22:58:07 +0530 | [diff] [blame] | 176 | } else if (board_is_k2g_ice() || board_is_k2g_i1()) { |
Cooper Jr., Franklin | 2b0273a | 2017-06-16 17:25:24 -0500 | [diff] [blame] | 177 | ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb); |
| 178 | ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_512mb); |
| 179 | } |
Vitaly Andrianov | bbf8ac2 | 2015-09-19 16:26:43 +0530 | [diff] [blame] | 180 | |
| 181 | return 0; |
| 182 | } |
| 183 | |
| 184 | inline int ddr3_get_size(void) |
| 185 | { |
| 186 | return 2; |
| 187 | } |