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Michal Simek4b066a12018-08-22 14:55:27 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2014 - 2018 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
5 */
6
7#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -07008#include <cpu_func.h>
Simon Glassed38aef2020-05-10 11:40:03 -06009#include <env.h>
Michal Simek4b066a12018-08-22 14:55:27 +020010#include <fdtdec.h>
Simon Glassa7b51302019-11-14 12:57:46 -070011#include <init.h>
Ashok Reddy Somafb6b3cd2021-02-23 08:07:46 -070012#include <env_internal.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
Michal Simek4b066a12018-08-22 14:55:27 +020014#include <malloc.h>
Simon Glass495a5dc2019-11-14 12:57:30 -070015#include <time.h>
Simon Glass274e0b02020-05-10 11:39:56 -060016#include <asm/cache.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060017#include <asm/global_data.h>
Michal Simek4b066a12018-08-22 14:55:27 +020018#include <asm/io.h>
19#include <asm/arch/hardware.h>
Michal Simek21eb5cc2019-04-29 09:39:09 -070020#include <asm/arch/sys_proto.h>
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +053021#include <dm/device.h>
22#include <dm/uclass.h>
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053023#include <versalpl.h>
Michal Simek705d44a2020-03-31 12:39:37 +020024#include "../common/board.h"
Michal Simek4b066a12018-08-22 14:55:27 +020025
26DECLARE_GLOBAL_DATA_PTR;
27
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053028#if defined(CONFIG_FPGA_VERSALPL)
Oleksandr Suvorovdae95a42022-07-22 17:16:04 +030029static xilinx_desc versalpl = {
30 xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
31 FPGA_LEGACY
32};
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053033#endif
34
Michal Simek4b066a12018-08-22 14:55:27 +020035int board_init(void)
36{
37 printf("EL Level:\tEL%d\n", current_el());
38
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053039#if defined(CONFIG_FPGA_VERSALPL)
40 fpga_init();
41 fpga_add(fpga_xilinx, &versalpl);
42#endif
43
Michal Simek394ee242020-08-03 13:01:45 +020044 if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
45 xilinx_read_eeprom();
46
Michal Simek4b066a12018-08-22 14:55:27 +020047 return 0;
48}
49
50int board_early_init_r(void)
51{
Michal Simek19f6c972019-01-28 11:08:00 +010052 u32 val;
Michal Simek4b066a12018-08-22 14:55:27 +020053
Michal Simek19f6c972019-01-28 11:08:00 +010054 if (current_el() != 3)
55 return 0;
Michal Simek4b066a12018-08-22 14:55:27 +020056
Michal Simekf56f7d12019-01-28 11:12:41 +010057 debug("iou_switch ctrl div0 %x\n",
58 readl(&crlapb_base->iou_switch_ctrl));
59
Michal Simek19f6c972019-01-28 11:08:00 +010060 writel(IOU_SWITCH_CTRL_CLKACT_BIT |
Michal Simekf56f7d12019-01-28 11:12:41 +010061 (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
Michal Simek19f6c972019-01-28 11:08:00 +010062 &crlapb_base->iou_switch_ctrl);
Michal Simek4b066a12018-08-22 14:55:27 +020063
Michal Simek19f6c972019-01-28 11:08:00 +010064 /* Global timer init - Program time stamp reference clk */
65 val = readl(&crlapb_base->timestamp_ref_ctrl);
66 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
67 writel(val, &crlapb_base->timestamp_ref_ctrl);
Michal Simek4b066a12018-08-22 14:55:27 +020068
Michal Simek19f6c972019-01-28 11:08:00 +010069 debug("ref ctrl 0x%x\n",
70 readl(&crlapb_base->timestamp_ref_ctrl));
Michal Simek4b066a12018-08-22 14:55:27 +020071
Michal Simek19f6c972019-01-28 11:08:00 +010072 /* Clear reset of timestamp reg */
73 writel(0, &crlapb_base->rst_timestamp);
Michal Simek4b066a12018-08-22 14:55:27 +020074
Michal Simek19f6c972019-01-28 11:08:00 +010075 /*
76 * Program freq register in System counter and
77 * enable system counter.
78 */
Peng Fan4b3a1822022-04-13 17:47:17 +080079 writel(CONFIG_COUNTER_FREQUENCY,
Michal Simek19f6c972019-01-28 11:08:00 +010080 &iou_scntr_secure->base_frequency_id_register);
Michal Simek4b066a12018-08-22 14:55:27 +020081
Michal Simek19f6c972019-01-28 11:08:00 +010082 debug("counter val 0x%x\n",
83 readl(&iou_scntr_secure->base_frequency_id_register));
84
85 writel(IOU_SCNTRS_CONTROL_EN,
86 &iou_scntr_secure->counter_control_register);
Michal Simek4b066a12018-08-22 14:55:27 +020087
Michal Simek19f6c972019-01-28 11:08:00 +010088 debug("scntrs control 0x%x\n",
89 readl(&iou_scntr_secure->counter_control_register));
90 debug("timer 0x%llx\n", get_ticks());
91 debug("timer 0x%llx\n", get_ticks());
Michal Simek4b066a12018-08-22 14:55:27 +020092
93 return 0;
94}
95
Ashok Reddy Soma6c191052022-05-05 23:53:45 -060096unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
97 char *const argv[])
98{
99 int ret = 0;
100
101 if (current_el() > 1) {
102 smp_kick_all_cpus();
103 dcache_disable();
104 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
105 ES_TO_AARCH64);
106 } else {
107 printf("FAIL: current EL is not above EL1\n");
108 ret = EINVAL;
109 }
110 return ret;
111}
112
Michal Simek9c91e612020-04-08 11:04:41 +0200113static u8 versal_get_bootmode(void)
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530114{
Michal Simek9c91e612020-04-08 11:04:41 +0200115 u8 bootmode;
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530116 u32 reg = 0;
Michal Simek9c91e612020-04-08 11:04:41 +0200117
118 reg = readl(&crp_base->boot_mode_usr);
119
120 if (reg >> BOOT_MODE_ALT_SHIFT)
121 reg >>= BOOT_MODE_ALT_SHIFT;
122
123 bootmode = reg & BOOT_MODES_MASK;
124
125 return bootmode;
126}
127
128int board_late_init(void)
129{
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530130 u8 bootmode;
131 struct udevice *dev;
132 int bootseq = -1;
133 int bootseq_len = 0;
134 int env_targets_len = 0;
135 const char *mode;
136 char *new_targets;
137 char *env_targets;
138
139 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
140 debug("Saved variables - Skipping\n");
141 return 0;
142 }
143
Michal Simekbab07b62020-07-28 12:45:47 +0200144 if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
145 return 0;
146
Michal Simek9c91e612020-04-08 11:04:41 +0200147 bootmode = versal_get_bootmode();
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530148
149 puts("Bootmode: ");
150 switch (bootmode) {
T Karthik Reddyfacca9a2019-07-11 16:07:57 +0530151 case USB_MODE:
152 puts("USB_MODE\n");
T Karthik Reddy1104faf2021-03-30 23:24:57 -0600153 mode = "usb_dfu0 usb_dfu1";
T Karthik Reddyfacca9a2019-07-11 16:07:57 +0530154 break;
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530155 case JTAG_MODE:
156 puts("JTAG_MODE\n");
Siva Durga Prasad Paladugu00784e02019-06-25 17:13:14 +0530157 mode = "jtag pxe dhcp";
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530158 break;
159 case QSPI_MODE_24BIT:
160 puts("QSPI_MODE_24\n");
161 mode = "xspi0";
162 break;
163 case QSPI_MODE_32BIT:
164 puts("QSPI_MODE_32\n");
165 mode = "xspi0";
166 break;
167 case OSPI_MODE:
168 puts("OSPI_MODE\n");
169 mode = "xspi0";
170 break;
171 case EMMC_MODE:
172 puts("EMMC_MODE\n");
T Karthik Reddybc2b9642019-12-16 04:44:26 -0700173 if (uclass_get_device_by_name(UCLASS_MMC,
T Karthik Reddya12445f2021-11-18 12:57:20 +0100174 "mmc@f1050000", &dev) &&
175 uclass_get_device_by_name(UCLASS_MMC,
T Karthik Reddybc2b9642019-12-16 04:44:26 -0700176 "sdhci@f1050000", &dev)) {
177 puts("Boot from EMMC but without SD1 enabled!\n");
178 return -1;
179 }
Simon Glass75e534b2020-12-16 21:20:07 -0700180 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
T Karthik Reddybc2b9642019-12-16 04:44:26 -0700181 mode = "mmc";
Simon Glass75e534b2020-12-16 21:20:07 -0700182 bootseq = dev_seq(dev);
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530183 break;
184 case SD_MODE:
185 puts("SD_MODE\n");
186 if (uclass_get_device_by_name(UCLASS_MMC,
T Karthik Reddya12445f2021-11-18 12:57:20 +0100187 "mmc@f1040000", &dev) &&
188 uclass_get_device_by_name(UCLASS_MMC,
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530189 "sdhci@f1040000", &dev)) {
190 puts("Boot from SD0 but without SD0 enabled!\n");
191 return -1;
192 }
Simon Glass75e534b2020-12-16 21:20:07 -0700193 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530194
195 mode = "mmc";
Simon Glass75e534b2020-12-16 21:20:07 -0700196 bootseq = dev_seq(dev);
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530197 break;
198 case SD1_LSHFT_MODE:
199 puts("LVL_SHFT_");
200 /* fall through */
201 case SD_MODE1:
202 puts("SD_MODE1\n");
203 if (uclass_get_device_by_name(UCLASS_MMC,
T Karthik Reddya12445f2021-11-18 12:57:20 +0100204 "mmc@f1050000", &dev) &&
205 uclass_get_device_by_name(UCLASS_MMC,
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530206 "sdhci@f1050000", &dev)) {
207 puts("Boot from SD1 but without SD1 enabled!\n");
208 return -1;
209 }
Simon Glass75e534b2020-12-16 21:20:07 -0700210 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530211
212 mode = "mmc";
Simon Glass75e534b2020-12-16 21:20:07 -0700213 bootseq = dev_seq(dev);
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530214 break;
215 default:
216 mode = "";
217 printf("Invalid Boot Mode:0x%x\n", bootmode);
218 break;
219 }
220
221 if (bootseq >= 0) {
222 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
223 debug("Bootseq len: %x\n", bootseq_len);
224 }
225
226 /*
227 * One terminating char + one byte for space between mode
228 * and default boot_targets
229 */
230 env_targets = env_get("boot_targets");
231 if (env_targets)
232 env_targets_len = strlen(env_targets);
233
234 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
235 bootseq_len);
236 if (!new_targets)
237 return -ENOMEM;
238
239 if (bootseq >= 0)
240 sprintf(new_targets, "%s%x %s", mode, bootseq,
241 env_targets ? env_targets : "");
242 else
243 sprintf(new_targets, "%s %s", mode,
244 env_targets ? env_targets : "");
245
246 env_set("boot_targets", new_targets);
247
Michal Simek705d44a2020-03-31 12:39:37 +0200248 return board_late_init_xilinx();
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530249}
250
Michal Simek4b066a12018-08-22 14:55:27 +0200251int dram_init_banksize(void)
252{
Michal Simek21eb5cc2019-04-29 09:39:09 -0700253 int ret;
254
255 ret = fdtdec_setup_memory_banksize();
256 if (ret)
257 return ret;
258
259 mem_map_fill();
Michal Simek4b066a12018-08-22 14:55:27 +0200260
261 return 0;
262}
263
264int dram_init(void)
265{
Michal Simek9134d4c2020-07-10 12:42:09 +0200266 if (fdtdec_setup_mem_size_base_lowest() != 0)
Michal Simek4b066a12018-08-22 14:55:27 +0200267 return -EINVAL;
268
269 return 0;
270}
271
Harald Seiler6f14d5f2020-12-15 16:47:52 +0100272void reset_cpu(void)
Michal Simek4b066a12018-08-22 14:55:27 +0200273{
274}
Ashok Reddy Somafb6b3cd2021-02-23 08:07:46 -0700275
276enum env_location env_get_location(enum env_operation op, int prio)
277{
278 u32 bootmode = versal_get_bootmode();
279
280 if (prio)
281 return ENVL_UNKNOWN;
282
283 switch (bootmode) {
284 case EMMC_MODE:
285 case SD_MODE:
286 case SD1_LSHFT_MODE:
287 case SD_MODE1:
288 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
289 return ENVL_FAT;
290 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
291 return ENVL_EXT4;
T Karthik Reddy6f8b2052021-11-24 12:16:55 +0100292 return ENVL_NOWHERE;
Ashok Reddy Somafb6b3cd2021-02-23 08:07:46 -0700293 case OSPI_MODE:
294 case QSPI_MODE_24BIT:
295 case QSPI_MODE_32BIT:
296 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
297 return ENVL_SPI_FLASH;
T Karthik Reddy6f8b2052021-11-24 12:16:55 +0100298 return ENVL_NOWHERE;
Ashok Reddy Somafb6b3cd2021-02-23 08:07:46 -0700299 case JTAG_MODE:
300 default:
301 return ENVL_NOWHERE;
302 }
303}