| Jim Liu | 147c000 | 2022-09-27 16:45:15 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | |
| 3 | #include <dt-bindings/reset/nuvoton,npcm8xx-reset.h> |
| 4 | |
| 5 | / { |
| 6 | #address-cells = <1>; |
| 7 | #size-cells = <1>; |
| 8 | interrupt-parent = <&gic>; |
| 9 | |
| 10 | /* external reference clock */ |
| 11 | clk_refclk: clk-refclk { |
| 12 | compatible = "fixed-clock"; |
| 13 | #clock-cells = <0>; |
| 14 | clock-frequency = <25000000>; |
| 15 | clock-output-names = "refclk"; |
| 16 | }; |
| 17 | |
| 18 | ahb { |
| 19 | rstc: reset-controller@f0801000 { |
| 20 | compatible = "nuvoton,npcm845-reset", "syscon", |
| 21 | "simple-mfd"; |
| 22 | reg = <0x0 0xf0801000 0x0 0xC4>; |
| 23 | rstc1: reset-controller1 { |
| 24 | compatible = "syscon-reset"; |
| 25 | #reset-cells = <1>; |
| 26 | regmap = <&rstc>; |
| 27 | offset = <NPCM8XX_RESET_IPSRST1>; |
| 28 | mask = <0xFFFFFFFF>; |
| 29 | }; |
| 30 | rstc2: reset-controller2 { |
| 31 | compatible = "syscon-reset"; |
| 32 | #reset-cells = <1>; |
| 33 | regmap = <&rstc>; |
| 34 | offset = <NPCM8XX_RESET_IPSRST2>; |
| 35 | mask = <0xFFFFFFFF>; |
| 36 | }; |
| 37 | rstc3: reset-controller3 { |
| 38 | compatible = "syscon-reset"; |
| 39 | #reset-cells = <1>; |
| 40 | regmap = <&rstc>; |
| 41 | offset = <NPCM8XX_RESET_IPSRST3>; |
| 42 | mask = <0xFFFFFFFF>; |
| 43 | }; |
| 44 | rstc4: reset-controller4 { |
| 45 | compatible = "syscon-reset"; |
| 46 | #reset-cells = <1>; |
| 47 | regmap = <&rstc>; |
| 48 | offset = <NPCM8XX_RESET_IPSRST4>; |
| 49 | mask = <0xFFFFFFFF>; |
| 50 | }; |
| 51 | }; |
| 52 | |
| 53 | clk: clock-controller@f0801000 { |
| 54 | compatible = "nuvoton,npcm845-clk", "syscon"; |
| 55 | #clock-cells = <1>; |
| 56 | clock-controller; |
| 57 | reg = <0x0 0xf0801000 0x0 0x1000>; |
| 58 | clock-names = "refclk"; |
| 59 | clocks = <&clk_refclk>; |
| 60 | }; |
| 61 | |
| 62 | apb { |
| 63 | serial0: serial@0 { |
| 64 | compatible = "nuvoton,npcm845-uart"; |
| 65 | reg = <0x0 0x1000>; |
| 66 | clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>; |
| 67 | clock-frequency = <24000000>; |
| 68 | status = "disabled"; |
| 69 | }; |
| 70 | |
| 71 | gpio0: gpio0@10000 { |
| 72 | compatible = "nuvoton,npcm-gpio"; |
| 73 | reg = <0x10000 0xB0>; |
| 74 | #gpio-cells = <2>; |
| 75 | gpio-controller; |
| 76 | gpio-bank-name = "gpio0"; |
| 77 | }; |
| 78 | |
| 79 | gpio1: gpio1@11000 { |
| 80 | compatible = "nuvoton,npcm-gpio"; |
| 81 | reg = <0x11000 0xB0>; |
| 82 | #gpio-cells = <2>; |
| 83 | gpio-controller; |
| 84 | gpio-bank-name = "gpio1"; |
| 85 | }; |
| 86 | |
| 87 | gpio2: gpio2@12000 { |
| 88 | compatible = "nuvoton,npcm-gpio"; |
| 89 | reg = <0x12000 0xB0>; |
| 90 | #gpio-cells = <2>; |
| 91 | gpio-controller; |
| 92 | gpio-bank-name = "gpio2"; |
| 93 | }; |
| 94 | |
| 95 | gpio3: gpio3@13000 { |
| 96 | compatible = "nuvoton,npcm-gpio"; |
| 97 | reg = <0x13000 0xB0>; |
| 98 | #gpio-cells = <2>; |
| 99 | gpio-controller; |
| 100 | gpio-bank-name = "gpio3"; |
| 101 | }; |
| 102 | |
| 103 | gpio4: gpio4@14000 { |
| 104 | compatible = "nuvoton,npcm-gpio"; |
| 105 | reg = <0x14000 0xB0>; |
| 106 | #gpio-cells = <2>; |
| 107 | gpio-controller; |
| 108 | gpio-bank-name = "gpio4"; |
| 109 | }; |
| 110 | |
| 111 | gpio5: gpio5@15000 { |
| 112 | compatible = "nuvoton,npcm-gpio"; |
| 113 | reg = <0x15000 0xB0>; |
| 114 | #gpio-cells = <2>; |
| 115 | gpio-controller; |
| 116 | gpio-bank-name = "gpio5"; |
| 117 | }; |
| 118 | |
| 119 | gpio6: gpio6@16000 { |
| 120 | compatible = "nuvoton,npcm-gpio"; |
| 121 | reg = <0x16000 0xB0>; |
| 122 | #gpio-cells = <2>; |
| 123 | gpio-controller; |
| 124 | gpio-bank-name = "gpio6"; |
| 125 | }; |
| 126 | |
| 127 | gpio7: gpio7@17000 { |
| 128 | compatible = "nuvoton,npcm-gpio"; |
| 129 | reg = <0x17000 0xB0>; |
| 130 | #gpio-cells = <2>; |
| 131 | gpio-controller; |
| 132 | gpio-bank-name = "gpio7"; |
| 133 | }; |
| 134 | }; |
| 135 | }; |
| 136 | }; |