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Ryan Mallon50515fa2011-06-05 07:21:22 +00001/*
2 * Bluewater Systems Snapper 9260 and 9G20 modules
3 *
4 * (C) Copyright 2011 Bluewater Systems
5 * Author: Andre Renaud <andre@bluewatersys.com>
6 * Author: Ryan Mallon <ryan@bluewatersys.com>
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Ryan Mallon50515fa2011-06-05 07:21:22 +00009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/* SoC type is defined in boards.cfg */
15#include <asm/hardware.h>
Alexey Brodkin267d8e22014-02-26 17:47:58 +040016#include <linux/sizes.h>
Ryan Mallon50515fa2011-06-05 07:21:22 +000017
Simon Glass26975992014-10-29 13:08:55 -060018#define CONFIG_SYS_TEXT_BASE 0x21f00000
Ryan Mallon50515fa2011-06-05 07:21:22 +000019
20/* ARM asynchronous clock */
21#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */
22#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
Ryan Mallon50515fa2011-06-05 07:21:22 +000023
24/* CPU */
25#define CONFIG_ARCH_CPU_INIT
Ryan Mallon50515fa2011-06-05 07:21:22 +000026
27#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
28#define CONFIG_SETUP_MEMORY_TAGS
29#define CONFIG_INITRD_TAG
30#define CONFIG_SKIP_LOWLEVEL_INIT
Ryan Mallon50515fa2011-06-05 07:21:22 +000031
32/* SDRAM */
33#define CONFIG_NR_DRAM_BANKS 1
34#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
35#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */
36#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
37 GENERATED_GBL_DATA_SIZE)
38
39/* Mem test settings */
40#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
41#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
42
43/* NAND Flash */
44#define CONFIG_NAND_ATMEL
Ryan Mallon50515fa2011-06-05 07:21:22 +000045#define CONFIG_SYS_MAX_NAND_DEVICE 1
46#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
47#define CONFIG_SYS_NAND_DBW_8
48#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
49#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
50#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
51#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
52
53/* Ethernet */
54#define CONFIG_MACB
55#define CONFIG_RMII
Ryan Mallon50515fa2011-06-05 07:21:22 +000056#define CONFIG_NET_RETRY_COUNT 20
57#define CONFIG_RESET_PHY_R
Heiko Schocher8a84ae12013-11-18 08:07:23 +010058#define CONFIG_AT91_WANTS_COMMON_PHY
Ryan Mallon50515fa2011-06-05 07:21:22 +000059#define CONFIG_TFTP_PORT
60#define CONFIG_TFTP_TSIZE
61
62/* USB */
63#define CONFIG_USB_ATMEL
Bo Shen4a985df2013-10-21 16:14:00 +080064#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Ryan Mallon50515fa2011-06-05 07:21:22 +000065#define CONFIG_USB_OHCI_NEW
Ryan Mallon50515fa2011-06-05 07:21:22 +000066#define CONFIG_SYS_USB_OHCI_CPU_INIT
67#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
68#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
69#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Ryan Mallon50515fa2011-06-05 07:21:22 +000070
71/* GPIOs and IO expander */
Ryan Mallon50515fa2011-06-05 07:21:22 +000072#define CONFIG_ATMEL_LEGACY
73#define CONFIG_AT91_GPIO
74#define CONFIG_AT91_GPIO_PULLUP 1
75#define CONFIG_PCA953X
76#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28
77#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} }
78
79/* UARTs/Serial console */
80#define CONFIG_ATMEL_USART
Simon Glass6d20e072014-10-29 13:09:01 -060081#ifndef CONFIG_DM_SERIAL
Ryan Mallon50515fa2011-06-05 07:21:22 +000082#define CONFIG_USART_BASE ATMEL_BASE_DBGU
83#define CONFIG_USART_ID ATMEL_ID_SYS
Simon Glass6d20e072014-10-29 13:09:01 -060084#endif
Ryan Mallon50515fa2011-06-05 07:21:22 +000085#define CONFIG_BAUDRATE 115200
Ryan Mallon50515fa2011-06-05 07:21:22 +000086
87/* I2C - Bit-bashed */
Heiko Schocher479a4cf2013-01-29 08:53:15 +010088#define CONFIG_SYS_I2C
89#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
90#define CONFIG_SYS_I2C_SOFT_SPEED 100000
91#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
Ryan Mallon50515fa2011-06-05 07:21:22 +000092#define CONFIG_SOFT_I2C_READ_REPEATED_START
Ryan Mallon50515fa2011-06-05 07:21:22 +000093#define I2C_INIT do { \
94 at91_set_gpio_output(AT91_PIN_PA23, 1); \
95 at91_set_gpio_output(AT91_PIN_PA24, 1); \
96 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
97 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
98 } while (0)
99#define I2C_SOFT_DECLARATIONS
100#define I2C_ACTIVE
101#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1);
102#define I2C_READ at91_get_gpio_value(AT91_PIN_PA23);
103#define I2C_SDA(bit) do { \
104 if (bit) { \
105 at91_set_gpio_input(AT91_PIN_PA23, 1); \
106 } else { \
107 at91_set_gpio_output(AT91_PIN_PA23, 1); \
108 at91_set_gpio_value(AT91_PIN_PA23, bit); \
109 } \
110 } while (0)
111#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
112#define I2C_DELAY udelay(2)
113
114/* Boot options */
115#define CONFIG_SYS_LOAD_ADDR 0x23000000
Ryan Mallon50515fa2011-06-05 07:21:22 +0000116
117#define CONFIG_BOOTP_BOOTFILESIZE
118#define CONFIG_BOOTP_BOOTPATH
119#define CONFIG_BOOTP_GATEWAY
120#define CONFIG_BOOTP_HOSTNAME
121
122/* Environment settings */
123#define CONFIG_ENV_IS_IN_NAND
124#define CONFIG_ENV_OFFSET (512 << 10)
125#define CONFIG_ENV_SIZE (256 << 10)
126#define CONFIG_ENV_OVERWRITE
127#define CONFIG_BOOTARGS "console=ttyS0,115200 ip=any"
128
129/* Console settings */
130#define CONFIG_SYS_CBSIZE 256
131#define CONFIG_SYS_MAXARGS 16
132#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
133 sizeof(CONFIG_SYS_PROMPT) + 16)
134#define CONFIG_SYS_LONGHELP
Ryan Mallon50515fa2011-06-05 07:21:22 +0000135#define CONFIG_CMDLINE_EDITING
136#define CONFIG_AUTO_COMPLETE
Ryan Mallon50515fa2011-06-05 07:21:22 +0000137
138/* U-Boot memory settings */
139#define CONFIG_SYS_MALLOC_LEN (1 << 20)
Ryan Mallon50515fa2011-06-05 07:21:22 +0000140
141/* Command line configuration */
Ryan Mallon50515fa2011-06-05 07:21:22 +0000142#define CONFIG_CMD_NAND
143#define CONFIG_CMD_PCA953X
144#define CONFIG_CMD_PCA953X_INFO
145
146#endif /* __CONFIG_H */