Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 1 | /* |
vijay rai | 27cdc77 | 2014-03-31 11:46:34 +0530 | [diff] [blame] | 2 | + * Copyright 2014 Freescale Semiconductor, Inc. |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: GPL-2.0+ |
| 5 | + */ |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 6 | |
| 7 | #ifndef __CONFIG_H |
| 8 | #define __CONFIG_H |
| 9 | |
| 10 | /* |
vijay rai | 27cdc77 | 2014-03-31 11:46:34 +0530 | [diff] [blame] | 11 | * T104x RDB board configuration file |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 12 | */ |
Prabhakar Kushwaha | c4c10d1 | 2014-10-29 22:33:09 +0530 | [diff] [blame] | 13 | #include <asm/config_mpc85xx.h> |
| 14 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 15 | #ifdef CONFIG_RAMBOOT_PBL |
Sumit Garg | afaca2a | 2016-07-14 12:27:52 -0400 | [diff] [blame] | 16 | |
| 17 | #ifndef CONFIG_SECURE_BOOT |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 18 | #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg |
Sumit Garg | afaca2a | 2016-07-14 12:27:52 -0400 | [diff] [blame] | 19 | #else |
| 20 | #define CONFIG_SYS_FSL_PBL_PBI \ |
| 21 | $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg |
| 22 | #endif |
| 23 | |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 24 | #define CONFIG_SPL_FLUSH_IMAGE |
| 25 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
Tang Yuantian | 25ccd5d | 2014-07-23 17:27:53 +0800 | [diff] [blame] | 26 | #define CONFIG_SYS_TEXT_BASE 0x30001000 |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 27 | #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 |
| 28 | #define CONFIG_SPL_PAD_TO 0x40000 |
| 29 | #define CONFIG_SPL_MAX_SIZE 0x28000 |
| 30 | #ifdef CONFIG_SPL_BUILD |
| 31 | #define CONFIG_SPL_SKIP_RELOCATE |
| 32 | #define CONFIG_SPL_COMMON_INIT_DDR |
| 33 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 34 | #endif |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 35 | #define RESET_VECTOR_OFFSET 0x27FFC |
| 36 | #define BOOT_PAGE_OFFSET 0x27000 |
| 37 | |
| 38 | #ifdef CONFIG_NAND |
Sumit Garg | afaca2a | 2016-07-14 12:27:52 -0400 | [diff] [blame] | 39 | #ifdef CONFIG_SECURE_BOOT |
| 40 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) |
| 41 | /* |
| 42 | * HDR would be appended at end of image and copied to DDR along |
| 43 | * with U-Boot image. |
| 44 | */ |
| 45 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ |
| 46 | CONFIG_U_BOOT_HDR_SIZE) |
| 47 | #else |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 48 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
Sumit Garg | afaca2a | 2016-07-14 12:27:52 -0400 | [diff] [blame] | 49 | #endif |
Tang Yuantian | 25ccd5d | 2014-07-23 17:27:53 +0800 | [diff] [blame] | 50 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 |
| 51 | #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 52 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) |
| 53 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" |
York Sun | 37cdf5d | 2016-11-18 13:31:27 -0800 | [diff] [blame] | 54 | #ifdef CONFIG_TARGET_T1040RDB |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 55 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 56 | $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg |
| 57 | #endif |
York Sun | e9c8dcf | 2016-11-18 13:44:00 -0800 | [diff] [blame] | 58 | #ifdef CONFIG_TARGET_T1042RDB_PI |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 59 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 60 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg |
| 61 | #endif |
York Sun | 5e47155 | 2016-11-21 11:08:49 -0800 | [diff] [blame] | 62 | #ifdef CONFIG_TARGET_T1042RDB |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 63 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 64 | $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg |
| 65 | #endif |
York Sun | 2c15601 | 2016-11-21 10:46:53 -0800 | [diff] [blame] | 66 | #ifdef CONFIG_TARGET_T1040D4RDB |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 67 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 68 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg |
| 69 | #endif |
York Sun | d08610d | 2016-11-21 11:04:34 -0800 | [diff] [blame] | 70 | #ifdef CONFIG_TARGET_T1042D4RDB |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 71 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 72 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg |
| 73 | #endif |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 74 | #define CONFIG_SPL_NAND_BOOT |
| 75 | #endif |
| 76 | |
| 77 | #ifdef CONFIG_SPIFLASH |
Tang Yuantian | 25ccd5d | 2014-07-23 17:27:53 +0800 | [diff] [blame] | 78 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 79 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
| 80 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) |
Tang Yuantian | 25ccd5d | 2014-07-23 17:27:53 +0800 | [diff] [blame] | 81 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) |
| 82 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 83 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) |
| 84 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" |
| 85 | #ifndef CONFIG_SPL_BUILD |
| 86 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| 87 | #endif |
York Sun | 37cdf5d | 2016-11-18 13:31:27 -0800 | [diff] [blame] | 88 | #ifdef CONFIG_TARGET_T1040RDB |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 89 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 90 | $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg |
| 91 | #endif |
York Sun | e9c8dcf | 2016-11-18 13:44:00 -0800 | [diff] [blame] | 92 | #ifdef CONFIG_TARGET_T1042RDB_PI |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 93 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 94 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg |
| 95 | #endif |
York Sun | 5e47155 | 2016-11-21 11:08:49 -0800 | [diff] [blame] | 96 | #ifdef CONFIG_TARGET_T1042RDB |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 97 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 98 | $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg |
| 99 | #endif |
York Sun | 2c15601 | 2016-11-21 10:46:53 -0800 | [diff] [blame] | 100 | #ifdef CONFIG_TARGET_T1040D4RDB |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 101 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 102 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg |
| 103 | #endif |
York Sun | d08610d | 2016-11-21 11:04:34 -0800 | [diff] [blame] | 104 | #ifdef CONFIG_TARGET_T1042D4RDB |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 105 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 106 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg |
| 107 | #endif |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 108 | #define CONFIG_SPL_SPI_BOOT |
| 109 | #endif |
| 110 | |
| 111 | #ifdef CONFIG_SDCARD |
Tang Yuantian | 25ccd5d | 2014-07-23 17:27:53 +0800 | [diff] [blame] | 112 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 113 | #define CONFIG_SPL_MMC_MINIMAL |
| 114 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
Tang Yuantian | 25ccd5d | 2014-07-23 17:27:53 +0800 | [diff] [blame] | 115 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) |
| 116 | #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 117 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) |
| 118 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" |
| 119 | #ifndef CONFIG_SPL_BUILD |
| 120 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| 121 | #endif |
York Sun | 37cdf5d | 2016-11-18 13:31:27 -0800 | [diff] [blame] | 122 | #ifdef CONFIG_TARGET_T1040RDB |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 123 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 124 | $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg |
| 125 | #endif |
York Sun | e9c8dcf | 2016-11-18 13:44:00 -0800 | [diff] [blame] | 126 | #ifdef CONFIG_TARGET_T1042RDB_PI |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 127 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 128 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg |
| 129 | #endif |
York Sun | 5e47155 | 2016-11-21 11:08:49 -0800 | [diff] [blame] | 130 | #ifdef CONFIG_TARGET_T1042RDB |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 131 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 132 | $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg |
| 133 | #endif |
York Sun | 2c15601 | 2016-11-21 10:46:53 -0800 | [diff] [blame] | 134 | #ifdef CONFIG_TARGET_T1040D4RDB |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 135 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 136 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg |
| 137 | #endif |
York Sun | d08610d | 2016-11-21 11:04:34 -0800 | [diff] [blame] | 138 | #ifdef CONFIG_TARGET_T1042D4RDB |
Zhao Qiang | 55107dc | 2016-09-08 12:55:32 +0800 | [diff] [blame] | 139 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 140 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg |
| 141 | #endif |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 142 | #define CONFIG_SPL_MMC_BOOT |
| 143 | #endif |
| 144 | |
| 145 | #endif |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 146 | |
| 147 | /* High Level Configuration Options */ |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 148 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 149 | #define CONFIG_MP /* support multiple processors */ |
| 150 | |
Tang Yuantian | 856b5f3 | 2014-04-17 15:33:45 +0800 | [diff] [blame] | 151 | /* support deep sleep */ |
| 152 | #define CONFIG_DEEP_SLEEP |
Tang Yuantian | 856b5f3 | 2014-04-17 15:33:45 +0800 | [diff] [blame] | 153 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 154 | #ifndef CONFIG_SYS_TEXT_BASE |
Prabhakar Kushwaha | f203656 | 2014-01-14 11:34:26 +0530 | [diff] [blame] | 155 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 156 | #endif |
| 157 | |
| 158 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 159 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
| 160 | #endif |
| 161 | |
| 162 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
York Sun | fe84507 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 163 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 164 | #define CONFIG_PCI_INDIRECT_BRIDGE |
Robert P. J. Day | a809981 | 2016-05-03 19:52:49 -0400 | [diff] [blame] | 165 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 166 | #define CONFIG_PCIE2 /* PCIE controller 2 */ |
| 167 | #define CONFIG_PCIE3 /* PCIE controller 3 */ |
| 168 | #define CONFIG_PCIE4 /* PCIE controller 4 */ |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 169 | |
| 170 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
| 171 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
| 172 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 173 | #define CONFIG_ENV_OVERWRITE |
| 174 | |
Masahiro Yamada | 8cea9b5 | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 175 | #ifdef CONFIG_MTD_NOR_FLASH |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 176 | #define CONFIG_FLASH_CFI_DRIVER |
| 177 | #define CONFIG_SYS_FLASH_CFI |
| 178 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| 179 | #endif |
| 180 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 181 | #if defined(CONFIG_SPIFLASH) |
| 182 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
| 183 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 184 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
| 185 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ |
| 186 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| 187 | #elif defined(CONFIG_SDCARD) |
| 188 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
| 189 | #define CONFIG_ENV_IS_IN_MMC |
| 190 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 191 | #define CONFIG_ENV_SIZE 0x2000 |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 192 | #define CONFIG_ENV_OFFSET (512 * 0x800) |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 193 | #elif defined(CONFIG_NAND) |
Sumit Garg | afaca2a | 2016-07-14 12:27:52 -0400 | [diff] [blame] | 194 | #ifdef CONFIG_SECURE_BOOT |
| 195 | #define CONFIG_RAMBOOT_NAND |
| 196 | #define CONFIG_BOOTSCRIPT_COPY_RAM |
| 197 | #endif |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 198 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
| 199 | #define CONFIG_ENV_IS_IN_NAND |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 200 | #define CONFIG_ENV_SIZE 0x2000 |
Prabhakar Kushwaha | f203656 | 2014-01-14 11:34:26 +0530 | [diff] [blame] | 201 | #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 202 | #else |
| 203 | #define CONFIG_ENV_IS_IN_FLASH |
| 204 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 205 | #define CONFIG_ENV_SIZE 0x2000 |
| 206 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
| 207 | #endif |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 208 | |
| 209 | #define CONFIG_SYS_CLK_FREQ 100000000 |
| 210 | #define CONFIG_DDR_CLK_FREQ 66666666 |
| 211 | |
| 212 | /* |
| 213 | * These can be toggled for performance analysis, otherwise use default. |
| 214 | */ |
| 215 | #define CONFIG_SYS_CACHE_STASHING |
| 216 | #define CONFIG_BACKSIDE_L2_CACHE |
| 217 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E |
| 218 | #define CONFIG_BTB /* toggle branch predition */ |
| 219 | #define CONFIG_DDR_ECC |
| 220 | #ifdef CONFIG_DDR_ECC |
| 221 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| 222 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
| 223 | #endif |
| 224 | |
| 225 | #define CONFIG_ENABLE_36BIT_PHYS |
| 226 | |
| 227 | #define CONFIG_ADDR_MAP |
| 228 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ |
| 229 | |
| 230 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
| 231 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
| 232 | #define CONFIG_SYS_ALT_MEMTEST |
| 233 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 234 | |
| 235 | /* |
| 236 | * Config the L3 Cache as L3 SRAM |
| 237 | */ |
| 238 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 |
Sumit Garg | afaca2a | 2016-07-14 12:27:52 -0400 | [diff] [blame] | 239 | /* |
| 240 | * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence |
| 241 | * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address |
| 242 | * (CONFIG_SYS_INIT_L3_VADDR) will be different. |
| 243 | */ |
| 244 | #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 245 | #define CONFIG_SYS_L3_SIZE 256 << 10 |
Sumit Garg | afaca2a | 2016-07-14 12:27:52 -0400 | [diff] [blame] | 246 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 247 | #ifdef CONFIG_RAMBOOT_PBL |
| 248 | #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) |
| 249 | #endif |
| 250 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) |
| 251 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) |
| 252 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) |
| 253 | #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 254 | |
| 255 | #define CONFIG_SYS_DCSRBAR 0xf0000000 |
| 256 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull |
| 257 | |
| 258 | /* |
| 259 | * DDR Setup |
| 260 | */ |
| 261 | #define CONFIG_VERY_BIG_RAM |
| 262 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 263 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 264 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 265 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
Priyanka Jain | 37e7f6a | 2014-02-26 09:38:37 +0530 | [diff] [blame] | 266 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 267 | |
| 268 | #define CONFIG_DDR_SPD |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 269 | |
| 270 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
| 271 | #define SPD_EEPROM_ADDRESS 0x51 |
| 272 | |
| 273 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
| 274 | |
| 275 | /* |
| 276 | * IFC Definitions |
| 277 | */ |
| 278 | #define CONFIG_SYS_FLASH_BASE 0xe8000000 |
| 279 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) |
| 280 | |
| 281 | #define CONFIG_SYS_NOR_CSPR_EXT (0xf) |
| 282 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ |
| 283 | CSPR_PORT_SIZE_16 | \ |
| 284 | CSPR_MSEL_NOR | \ |
| 285 | CSPR_V) |
| 286 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
Sandeep Singh | 4fb16a1 | 2014-06-05 18:49:57 +0530 | [diff] [blame] | 287 | |
| 288 | /* |
| 289 | * TDM Definition |
| 290 | */ |
| 291 | #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 |
| 292 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 293 | /* NOR Flash Timing Params */ |
| 294 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 |
| 295 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
| 296 | FTIM0_NOR_TEADC(0x5) | \ |
| 297 | FTIM0_NOR_TEAHC(0x5)) |
| 298 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
| 299 | FTIM1_NOR_TRAD_NOR(0x1A) |\ |
| 300 | FTIM1_NOR_TSEQRAD_NOR(0x13)) |
| 301 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ |
| 302 | FTIM2_NOR_TCH(0x4) | \ |
| 303 | FTIM2_NOR_TWPH(0x0E) | \ |
| 304 | FTIM2_NOR_TWP(0x1c)) |
| 305 | #define CONFIG_SYS_NOR_FTIM3 0x0 |
| 306 | |
| 307 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 308 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 309 | |
| 310 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 311 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| 312 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 313 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 314 | |
| 315 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 316 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
| 317 | |
| 318 | /* CPLD on IFC */ |
Prabhakar Kushwaha | e5e6633 | 2014-04-03 16:50:05 +0530 | [diff] [blame] | 319 | #define CPLD_LBMAP_MASK 0x3F |
| 320 | #define CPLD_BANK_SEL_MASK 0x07 |
| 321 | #define CPLD_BANK_OVERRIDE 0x40 |
| 322 | #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ |
| 323 | #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ |
| 324 | #define CPLD_LBMAP_RESET 0xFF |
| 325 | #define CPLD_LBMAP_SHIFT 0x03 |
Priyanka Jain | e7597fe | 2015-06-05 15:29:02 +0530 | [diff] [blame] | 326 | |
York Sun | e9c8dcf | 2016-11-18 13:44:00 -0800 | [diff] [blame] | 327 | #if defined(CONFIG_TARGET_T1042RDB_PI) |
Jason Jin | dd6377a | 2014-03-19 10:47:56 +0800 | [diff] [blame] | 328 | #define CPLD_DIU_SEL_DFP 0x80 |
York Sun | d08610d | 2016-11-21 11:04:34 -0800 | [diff] [blame] | 329 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
Priyanka Jain | e7597fe | 2015-06-05 15:29:02 +0530 | [diff] [blame] | 330 | #define CPLD_DIU_SEL_DFP 0xc0 |
Jason Jin | dd6377a | 2014-03-19 10:47:56 +0800 | [diff] [blame] | 331 | #endif |
Prabhakar Kushwaha | e5e6633 | 2014-04-03 16:50:05 +0530 | [diff] [blame] | 332 | |
York Sun | 2c15601 | 2016-11-21 10:46:53 -0800 | [diff] [blame] | 333 | #if defined(CONFIG_TARGET_T1040D4RDB) |
Priyanka Jain | e7597fe | 2015-06-05 15:29:02 +0530 | [diff] [blame] | 334 | #define CPLD_INT_MASK_ALL 0xFF |
| 335 | #define CPLD_INT_MASK_THERM 0x80 |
| 336 | #define CPLD_INT_MASK_DVI_DFP 0x40 |
| 337 | #define CPLD_INT_MASK_QSGMII1 0x20 |
| 338 | #define CPLD_INT_MASK_QSGMII2 0x10 |
| 339 | #define CPLD_INT_MASK_SGMI1 0x08 |
| 340 | #define CPLD_INT_MASK_SGMI2 0x04 |
| 341 | #define CPLD_INT_MASK_TDMR1 0x02 |
| 342 | #define CPLD_INT_MASK_TDMR2 0x01 |
| 343 | #endif |
| 344 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 345 | #define CONFIG_SYS_CPLD_BASE 0xffdf0000 |
| 346 | #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) |
Priyanka Jain | 9495ef3 | 2014-01-27 14:07:11 +0530 | [diff] [blame] | 347 | #define CONFIG_SYS_CSPR2_EXT (0xf) |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 348 | #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ |
| 349 | | CSPR_PORT_SIZE_8 \ |
| 350 | | CSPR_MSEL_GPCM \ |
| 351 | | CSPR_V) |
| 352 | #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) |
| 353 | #define CONFIG_SYS_CSOR2 0x0 |
| 354 | /* CPLD Timing parameters for IFC CS2 */ |
| 355 | #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ |
| 356 | FTIM0_GPCM_TEADC(0x0e) | \ |
| 357 | FTIM0_GPCM_TEAHC(0x0e)) |
| 358 | #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ |
| 359 | FTIM1_GPCM_TRAD(0x1f)) |
| 360 | #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ |
Shaohui Xie | c2bc460 | 2014-06-26 14:41:33 +0800 | [diff] [blame] | 361 | FTIM2_GPCM_TCH(0x8) | \ |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 362 | FTIM2_GPCM_TWP(0x1f)) |
| 363 | #define CONFIG_SYS_CS2_FTIM3 0x0 |
| 364 | |
| 365 | /* NAND Flash on IFC */ |
| 366 | #define CONFIG_NAND_FSL_IFC |
| 367 | #define CONFIG_SYS_NAND_BASE 0xff800000 |
| 368 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) |
| 369 | |
| 370 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) |
| 371 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 372 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ |
| 373 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ |
| 374 | | CSPR_V) |
| 375 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
| 376 | |
| 377 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 378 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 379 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
| 380 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ |
| 381 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ |
| 382 | | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ |
| 383 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ |
| 384 | |
| 385 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| 386 | |
| 387 | /* ONFI NAND Flash mode0 Timing Params */ |
| 388 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ |
| 389 | FTIM0_NAND_TWP(0x18) | \ |
| 390 | FTIM0_NAND_TWCHT(0x07) | \ |
| 391 | FTIM0_NAND_TWH(0x0a)) |
| 392 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
| 393 | FTIM1_NAND_TWBE(0x39) | \ |
| 394 | FTIM1_NAND_TRR(0x0e) | \ |
| 395 | FTIM1_NAND_TRP(0x18)) |
| 396 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ |
| 397 | FTIM2_NAND_TREH(0x0a) | \ |
| 398 | FTIM2_NAND_TWHRE(0x1e)) |
| 399 | #define CONFIG_SYS_NAND_FTIM3 0x0 |
| 400 | |
| 401 | #define CONFIG_SYS_NAND_DDR_LAW 11 |
| 402 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
| 403 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 404 | #define CONFIG_CMD_NAND |
| 405 | |
| 406 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) |
| 407 | |
| 408 | #if defined(CONFIG_NAND) |
| 409 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 410 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| 411 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
| 412 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
| 413 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 414 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 415 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 416 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 417 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT |
| 418 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR |
| 419 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK |
| 420 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
| 421 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 422 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 423 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 424 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 425 | #else |
| 426 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT |
| 427 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
| 428 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
| 429 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
| 430 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 431 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 432 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 433 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 434 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 435 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR |
| 436 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK |
| 437 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR |
| 438 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 439 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 440 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 441 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 442 | #endif |
| 443 | |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 444 | #ifdef CONFIG_SPL_BUILD |
| 445 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE |
| 446 | #else |
| 447 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 448 | #endif |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 449 | |
| 450 | #if defined(CONFIG_RAMBOOT_PBL) |
| 451 | #define CONFIG_SYS_RAMBOOT |
| 452 | #endif |
| 453 | |
Prabhakar Kushwaha | c4c10d1 | 2014-10-29 22:33:09 +0530 | [diff] [blame] | 454 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 |
| 455 | #if defined(CONFIG_NAND) |
| 456 | #define CONFIG_A008044_WORKAROUND |
| 457 | #endif |
| 458 | #endif |
| 459 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 460 | #define CONFIG_BOARD_EARLY_INIT_R |
| 461 | #define CONFIG_MISC_INIT_R |
| 462 | |
| 463 | #define CONFIG_HWCONFIG |
| 464 | |
| 465 | /* define to use L1 as initial stack */ |
| 466 | #define CONFIG_L1_INIT_RAM |
| 467 | #define CONFIG_SYS_INIT_RAM_LOCK |
| 468 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ |
| 469 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
York Sun | ee7b483 | 2015-08-17 13:31:51 -0700 | [diff] [blame] | 470 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 471 | /* The assembler doesn't like typecast */ |
| 472 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ |
| 473 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ |
| 474 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) |
| 475 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
| 476 | |
| 477 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
| 478 | GENERATED_GBL_DATA_SIZE) |
| 479 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 480 | |
Prabhakar Kushwaha | f402731 | 2014-03-31 15:31:48 +0530 | [diff] [blame] | 481 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 482 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
| 483 | |
| 484 | /* Serial Port - controlled on board with jumper J8 |
| 485 | * open - index 2 |
| 486 | * shorted - index 1 |
| 487 | */ |
| 488 | #define CONFIG_CONS_INDEX 1 |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 489 | #define CONFIG_SYS_NS16550_SERIAL |
| 490 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 491 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) |
| 492 | |
| 493 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 494 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
| 495 | |
| 496 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) |
| 497 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) |
| 498 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) |
| 499 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 500 | |
York Sun | d08610d | 2016-11-21 11:04:34 -0800 | [diff] [blame] | 501 | #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) |
Jason Jin | dd6377a | 2014-03-19 10:47:56 +0800 | [diff] [blame] | 502 | /* Video */ |
| 503 | #define CONFIG_FSL_DIU_FB |
| 504 | |
| 505 | #ifdef CONFIG_FSL_DIU_FB |
| 506 | #define CONFIG_FSL_DIU_CH7301 |
| 507 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) |
Jason Jin | dd6377a | 2014-03-19 10:47:56 +0800 | [diff] [blame] | 508 | #define CONFIG_CMD_BMP |
Jason Jin | dd6377a | 2014-03-19 10:47:56 +0800 | [diff] [blame] | 509 | #define CONFIG_VIDEO_LOGO |
| 510 | #define CONFIG_VIDEO_BMP_LOGO |
| 511 | #endif |
| 512 | #endif |
| 513 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 514 | /* I2C */ |
| 515 | #define CONFIG_SYS_I2C |
| 516 | #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ |
| 517 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ |
Shengzhou Liu | f7ce895 | 2014-07-07 12:17:47 +0800 | [diff] [blame] | 518 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
| 519 | #define CONFIG_SYS_FSL_I2C3_SPEED 400000 |
| 520 | #define CONFIG_SYS_FSL_I2C4_SPEED 400000 |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 521 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 522 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
Shengzhou Liu | f7ce895 | 2014-07-07 12:17:47 +0800 | [diff] [blame] | 523 | #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F |
| 524 | #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 525 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
Shengzhou Liu | f7ce895 | 2014-07-07 12:17:47 +0800 | [diff] [blame] | 526 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 |
| 527 | #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 |
| 528 | #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 529 | |
| 530 | /* I2C bus multiplexer */ |
| 531 | #define I2C_MUX_PCA_ADDR 0x70 |
| 532 | #define I2C_MUX_CH_DEFAULT 0x8 |
vijay rai | 27cdc77 | 2014-03-31 11:46:34 +0530 | [diff] [blame] | 533 | |
York Sun | 097aa60 | 2016-11-21 11:25:26 -0800 | [diff] [blame] | 534 | #if defined(CONFIG_TARGET_T1042RDB_PI) || \ |
| 535 | defined(CONFIG_TARGET_T1040D4RDB) || \ |
| 536 | defined(CONFIG_TARGET_T1042D4RDB) |
Jason Jin | dd6377a | 2014-03-19 10:47:56 +0800 | [diff] [blame] | 537 | /* LDI/DVI Encoder for display */ |
| 538 | #define CONFIG_SYS_I2C_LDI_ADDR 0x38 |
| 539 | #define CONFIG_SYS_I2C_DVI_ADDR 0x75 |
| 540 | |
vijay rai | 27cdc77 | 2014-03-31 11:46:34 +0530 | [diff] [blame] | 541 | /* |
| 542 | * RTC configuration |
| 543 | */ |
| 544 | #define RTC |
| 545 | #define CONFIG_RTC_DS1337 1 |
| 546 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 547 | |
vijay rai | 27cdc77 | 2014-03-31 11:46:34 +0530 | [diff] [blame] | 548 | /*DVI encoder*/ |
| 549 | #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 |
| 550 | #endif |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 551 | |
| 552 | /* |
| 553 | * eSPI - Enhanced SPI |
| 554 | */ |
Zhiqiang Hou | 4223c3d | 2014-09-17 17:37:44 +0800 | [diff] [blame] | 555 | #define CONFIG_SPI_FLASH_BAR |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 556 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
| 557 | #define CONFIG_SF_DEFAULT_MODE 0 |
Priyanka Jain | 9495ef3 | 2014-01-27 14:07:11 +0530 | [diff] [blame] | 558 | #define CONFIG_ENV_SPI_BUS 0 |
| 559 | #define CONFIG_ENV_SPI_CS 0 |
| 560 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 |
| 561 | #define CONFIG_ENV_SPI_MODE 0 |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 562 | |
| 563 | /* |
| 564 | * General PCI |
| 565 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 566 | */ |
| 567 | |
| 568 | #ifdef CONFIG_PCI |
| 569 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ |
| 570 | #ifdef CONFIG_PCIE1 |
| 571 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
| 572 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
| 573 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
| 574 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ |
| 575 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 |
| 576 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 577 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
| 578 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| 579 | #endif |
| 580 | |
| 581 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ |
| 582 | #ifdef CONFIG_PCIE2 |
| 583 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 |
| 584 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
| 585 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull |
| 586 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ |
| 587 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 |
| 588 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| 589 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
| 590 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| 591 | #endif |
| 592 | |
| 593 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ |
| 594 | #ifdef CONFIG_PCIE3 |
| 595 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 |
| 596 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
| 597 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull |
| 598 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ |
| 599 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 |
| 600 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
| 601 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull |
| 602 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
| 603 | #endif |
| 604 | |
| 605 | /* controller 4, Base address 203000 */ |
| 606 | #ifdef CONFIG_PCIE4 |
| 607 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 |
| 608 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 |
| 609 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull |
| 610 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ |
| 611 | #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 |
| 612 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 |
| 613 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull |
| 614 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ |
| 615 | #endif |
| 616 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 617 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 618 | #endif /* CONFIG_PCI */ |
| 619 | |
| 620 | /* SATA */ |
| 621 | #define CONFIG_FSL_SATA_V2 |
| 622 | #ifdef CONFIG_FSL_SATA_V2 |
| 623 | #define CONFIG_LIBATA |
| 624 | #define CONFIG_FSL_SATA |
| 625 | |
| 626 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
| 627 | #define CONFIG_SATA1 |
| 628 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
| 629 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA |
| 630 | |
| 631 | #define CONFIG_LBA48 |
| 632 | #define CONFIG_CMD_SATA |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 633 | #endif |
| 634 | |
| 635 | /* |
| 636 | * USB |
| 637 | */ |
| 638 | #define CONFIG_HAS_FSL_DR_USB |
| 639 | |
| 640 | #ifdef CONFIG_HAS_FSL_DR_USB |
| 641 | #define CONFIG_USB_EHCI |
| 642 | |
| 643 | #ifdef CONFIG_USB_EHCI |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 644 | #define CONFIG_USB_EHCI_FSL |
| 645 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 646 | #endif |
| 647 | #endif |
| 648 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 649 | #ifdef CONFIG_MMC |
| 650 | #define CONFIG_FSL_ESDHC |
| 651 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 652 | #endif |
| 653 | |
| 654 | /* Qman/Bman */ |
| 655 | #ifndef CONFIG_NOBQFMAN |
| 656 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ |
Jeffrey Ladouceur | f9c3974 | 2014-12-03 18:08:43 -0500 | [diff] [blame] | 657 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 658 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
| 659 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull |
| 660 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 |
Jeffrey Ladouceur | ff2c646 | 2014-12-08 14:54:01 -0500 | [diff] [blame] | 661 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
| 662 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 |
| 663 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE |
| 664 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) |
| 665 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ |
| 666 | CONFIG_SYS_BMAN_CENA_SIZE) |
| 667 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) |
| 668 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 |
Jeffrey Ladouceur | f9c3974 | 2014-12-03 18:08:43 -0500 | [diff] [blame] | 669 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 670 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
| 671 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull |
| 672 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 |
Jeffrey Ladouceur | ff2c646 | 2014-12-08 14:54:01 -0500 | [diff] [blame] | 673 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
| 674 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 |
| 675 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE |
| 676 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) |
| 677 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ |
| 678 | CONFIG_SYS_QMAN_CENA_SIZE) |
| 679 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) |
| 680 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 681 | |
| 682 | #define CONFIG_SYS_DPAA_FMAN |
| 683 | #define CONFIG_SYS_DPAA_PME |
| 684 | |
Zhao Qiang | 3c49424 | 2014-03-14 10:11:03 +0800 | [diff] [blame] | 685 | #define CONFIG_QE |
| 686 | #define CONFIG_U_QE |
| 687 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 688 | /* Default address of microcode for the Linux Fman driver */ |
| 689 | #if defined(CONFIG_SPIFLASH) |
| 690 | /* |
| 691 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after |
| 692 | * env, so we got 0x110000. |
| 693 | */ |
| 694 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH |
Zhao Qiang | 83a9084 | 2014-03-21 16:21:44 +0800 | [diff] [blame] | 695 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 696 | #elif defined(CONFIG_SDCARD) |
| 697 | /* |
| 698 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 699 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is |
| 700 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 701 | */ |
| 702 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 703 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 704 | #elif defined(CONFIG_NAND) |
| 705 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 706 | #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 707 | #else |
| 708 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
Zhao Qiang | 83a9084 | 2014-03-21 16:21:44 +0800 | [diff] [blame] | 709 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 710 | #endif |
| 711 | |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 712 | #if defined(CONFIG_SPIFLASH) |
| 713 | #define CONFIG_SYS_QE_FW_ADDR 0x130000 |
| 714 | #elif defined(CONFIG_SDCARD) |
| 715 | #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) |
| 716 | #elif defined(CONFIG_NAND) |
| 717 | #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| 718 | #else |
Zhao Qiang | 3c49424 | 2014-03-14 10:11:03 +0800 | [diff] [blame] | 719 | #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 720 | #endif |
Prabhakar Kushwaha | c8d8e1a | 2014-04-08 19:13:56 +0530 | [diff] [blame] | 721 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 722 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
| 723 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |
| 724 | #endif /* CONFIG_NOBQFMAN */ |
| 725 | |
| 726 | #ifdef CONFIG_SYS_DPAA_FMAN |
| 727 | #define CONFIG_FMAN_ENET |
| 728 | #define CONFIG_PHY_VITESSE |
| 729 | #define CONFIG_PHY_REALTEK |
| 730 | #endif |
| 731 | |
| 732 | #ifdef CONFIG_FMAN_ENET |
York Sun | 5e47155 | 2016-11-21 11:08:49 -0800 | [diff] [blame] | 733 | #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) |
Priyanka Jain | e7597fe | 2015-06-05 15:29:02 +0530 | [diff] [blame] | 734 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 |
York Sun | 2c15601 | 2016-11-21 10:46:53 -0800 | [diff] [blame] | 735 | #elif defined(CONFIG_TARGET_T1040D4RDB) |
Codrin Ciubotariu | d456ea1 | 2015-10-12 16:33:13 +0300 | [diff] [blame] | 736 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 |
York Sun | d08610d | 2016-11-21 11:04:34 -0800 | [diff] [blame] | 737 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
Priyanka Jain | e7597fe | 2015-06-05 15:29:02 +0530 | [diff] [blame] | 738 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 |
| 739 | #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 |
| 740 | #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 |
| 741 | #endif |
| 742 | |
York Sun | 097aa60 | 2016-11-21 11:25:26 -0800 | [diff] [blame] | 743 | #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) |
Priyanka Jain | e7597fe | 2015-06-05 15:29:02 +0530 | [diff] [blame] | 744 | #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 |
| 745 | #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 |
| 746 | #else |
| 747 | #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 |
| 748 | #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 |
vijay rai | 27cdc77 | 2014-03-31 11:46:34 +0530 | [diff] [blame] | 749 | #endif |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 750 | |
Codrin Ciubotariu | b29e5e2 | 2015-01-21 11:54:12 +0200 | [diff] [blame] | 751 | /* Enable VSC9953 L2 Switch driver on T1040 SoC */ |
York Sun | 37cdf5d | 2016-11-18 13:31:27 -0800 | [diff] [blame] | 752 | #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) |
Codrin Ciubotariu | b29e5e2 | 2015-01-21 11:54:12 +0200 | [diff] [blame] | 753 | #define CONFIG_VSC9953 |
Codrin Ciubotariu | 2f52a3f | 2015-07-24 16:55:28 +0300 | [diff] [blame] | 754 | #define CONFIG_CMD_ETHSW |
York Sun | 37cdf5d | 2016-11-18 13:31:27 -0800 | [diff] [blame] | 755 | #ifdef CONFIG_TARGET_T1040RDB |
Codrin Ciubotariu | b29e5e2 | 2015-01-21 11:54:12 +0200 | [diff] [blame] | 756 | #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 |
| 757 | #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 |
Priyanka Jain | e7597fe | 2015-06-05 15:29:02 +0530 | [diff] [blame] | 758 | #else |
| 759 | #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 |
| 760 | #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c |
| 761 | #endif |
Codrin Ciubotariu | b29e5e2 | 2015-01-21 11:54:12 +0200 | [diff] [blame] | 762 | #endif |
| 763 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 764 | #define CONFIG_MII /* MII PHY management */ |
Priyanka Jain | 29b426b | 2014-01-30 11:30:04 +0530 | [diff] [blame] | 765 | #define CONFIG_ETHPRIME "FM1@DTSEC4" |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 766 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
| 767 | #endif |
| 768 | |
| 769 | /* |
| 770 | * Environment |
| 771 | */ |
| 772 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ |
| 773 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
| 774 | |
| 775 | /* |
| 776 | * Command line configuration. |
| 777 | */ |
York Sun | e9c8dcf | 2016-11-18 13:44:00 -0800 | [diff] [blame] | 778 | #ifdef CONFIG_TARGET_T1042RDB_PI |
vijay rai | 27cdc77 | 2014-03-31 11:46:34 +0530 | [diff] [blame] | 779 | #define CONFIG_CMD_DATE |
| 780 | #endif |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 781 | #define CONFIG_CMD_ERRATA |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 782 | #define CONFIG_CMD_IRQ |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 783 | #define CONFIG_CMD_REGINFO |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 784 | |
| 785 | #ifdef CONFIG_PCI |
| 786 | #define CONFIG_CMD_PCI |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 787 | #endif |
| 788 | |
Ruchika Gupta | 12af67f | 2014-10-15 11:35:31 +0530 | [diff] [blame] | 789 | /* Hash command with SHA acceleration supported in hardware */ |
| 790 | #ifdef CONFIG_FSL_CAAM |
| 791 | #define CONFIG_CMD_HASH |
| 792 | #define CONFIG_SHA_HW_ACCEL |
| 793 | #endif |
| 794 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 795 | /* |
| 796 | * Miscellaneous configurable options |
| 797 | */ |
| 798 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 799 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 800 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
| 801 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 802 | #ifdef CONFIG_CMD_KGDB |
| 803 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 804 | #else |
| 805 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 806 | #endif |
| 807 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
| 808 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 809 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 810 | |
| 811 | /* |
| 812 | * For booting Linux, the board info and command line data |
| 813 | * have to be in the first 64 MB of memory, since this is |
| 814 | * the maximum mapped by the Linux kernel during initialization. |
| 815 | */ |
| 816 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ |
| 817 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| 818 | |
| 819 | #ifdef CONFIG_CMD_KGDB |
| 820 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 821 | #endif |
| 822 | |
| 823 | /* |
Prabhakar Kushwaha | 3d1b4bf | 2014-04-02 17:26:23 +0530 | [diff] [blame] | 824 | * Dynamic MTD Partition support with mtdparts |
| 825 | */ |
Masahiro Yamada | 8cea9b5 | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 826 | #ifdef CONFIG_MTD_NOR_FLASH |
Prabhakar Kushwaha | 3d1b4bf | 2014-04-02 17:26:23 +0530 | [diff] [blame] | 827 | #define CONFIG_MTD_DEVICE |
| 828 | #define CONFIG_MTD_PARTITIONS |
| 829 | #define CONFIG_CMD_MTDPARTS |
| 830 | #define CONFIG_FLASH_CFI_MTD |
| 831 | #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ |
| 832 | "spi0=spife110000.0" |
| 833 | #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ |
| 834 | "128k(dtb),96m(fs),-(user);"\ |
| 835 | "fff800000.flash:2m(uboot),9m(kernel),"\ |
| 836 | "128k(dtb),96m(fs),-(user);spife110000.0:" \ |
| 837 | "2m(uboot),9m(kernel),128k(dtb),-(user)" |
| 838 | #endif |
| 839 | |
| 840 | /* |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 841 | * Environment Configuration |
| 842 | */ |
| 843 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| 844 | #define CONFIG_BOOTFILE "uImage" |
| 845 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ |
| 846 | |
| 847 | /* default location for tftp and bootm */ |
| 848 | #define CONFIG_LOADADDR 1000000 |
| 849 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 850 | |
| 851 | #define CONFIG_BAUDRATE 115200 |
| 852 | |
| 853 | #define __USB_PHY_TYPE utmi |
vijay rai | 6eb8e0c | 2014-08-19 12:46:53 +0530 | [diff] [blame] | 854 | #define RAMDISKFILE "t104xrdb/ramdisk.uboot" |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 855 | |
York Sun | 37cdf5d | 2016-11-18 13:31:27 -0800 | [diff] [blame] | 856 | #ifdef CONFIG_TARGET_T1040RDB |
vijay rai | 27cdc77 | 2014-03-31 11:46:34 +0530 | [diff] [blame] | 857 | #define FDTFILE "t1040rdb/t1040rdb.dtb" |
York Sun | e9c8dcf | 2016-11-18 13:44:00 -0800 | [diff] [blame] | 858 | #elif defined(CONFIG_TARGET_T1042RDB_PI) |
vijay rai | 6eb8e0c | 2014-08-19 12:46:53 +0530 | [diff] [blame] | 859 | #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" |
York Sun | 5e47155 | 2016-11-21 11:08:49 -0800 | [diff] [blame] | 860 | #elif defined(CONFIG_TARGET_T1042RDB) |
vijay rai | 6eb8e0c | 2014-08-19 12:46:53 +0530 | [diff] [blame] | 861 | #define FDTFILE "t1042rdb/t1042rdb.dtb" |
York Sun | 2c15601 | 2016-11-21 10:46:53 -0800 | [diff] [blame] | 862 | #elif defined(CONFIG_TARGET_T1040D4RDB) |
Priyanka Jain | e7597fe | 2015-06-05 15:29:02 +0530 | [diff] [blame] | 863 | #define FDTFILE "t1042rdb/t1040d4rdb.dtb" |
York Sun | d08610d | 2016-11-21 11:04:34 -0800 | [diff] [blame] | 864 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
Priyanka Jain | e7597fe | 2015-06-05 15:29:02 +0530 | [diff] [blame] | 865 | #define FDTFILE "t1042rdb/t1042d4rdb.dtb" |
vijay rai | 27cdc77 | 2014-03-31 11:46:34 +0530 | [diff] [blame] | 866 | #endif |
| 867 | |
Jason Jin | dd6377a | 2014-03-19 10:47:56 +0800 | [diff] [blame] | 868 | #ifdef CONFIG_FSL_DIU_FB |
| 869 | #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" |
| 870 | #else |
| 871 | #define DIU_ENVIRONMENT |
| 872 | #endif |
| 873 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 874 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Priyanka Jain | 9495ef3 | 2014-01-27 14:07:11 +0530 | [diff] [blame] | 875 | "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ |
| 876 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ |
| 877 | "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 878 | "netdev=eth0\0" \ |
Jason Jin | dd6377a | 2014-03-19 10:47:56 +0800 | [diff] [blame] | 879 | "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 880 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 881 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ |
| 882 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
| 883 | "protect off $ubootaddr +$filesize && " \ |
| 884 | "erase $ubootaddr +$filesize && " \ |
| 885 | "cp.b $loadaddr $ubootaddr $filesize && " \ |
| 886 | "protect on $ubootaddr +$filesize && " \ |
| 887 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ |
| 888 | "consoledev=ttyS0\0" \ |
| 889 | "ramdiskaddr=2000000\0" \ |
vijay rai | 27cdc77 | 2014-03-31 11:46:34 +0530 | [diff] [blame] | 890 | "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ |
Scott Wood | b7f4b85 | 2016-07-19 17:52:06 -0500 | [diff] [blame] | 891 | "fdtaddr=1e00000\0" \ |
vijay rai | 27cdc77 | 2014-03-31 11:46:34 +0530 | [diff] [blame] | 892 | "fdtfile=" __stringify(FDTFILE) "\0" \ |
Kim Phillips | 1dedccc | 2014-05-14 19:33:45 -0500 | [diff] [blame] | 893 | "bdev=sda3\0" |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 894 | |
| 895 | #define CONFIG_LINUX \ |
| 896 | "setenv bootargs root=/dev/ram rw " \ |
| 897 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 898 | "setenv ramdiskaddr 0x02000000;" \ |
| 899 | "setenv fdtaddr 0x00c00000;" \ |
| 900 | "setenv loadaddr 0x1000000;" \ |
| 901 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| 902 | |
| 903 | #define CONFIG_HDBOOT \ |
| 904 | "setenv bootargs root=/dev/$bdev rw " \ |
| 905 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 906 | "tftp $loadaddr $bootfile;" \ |
| 907 | "tftp $fdtaddr $fdtfile;" \ |
| 908 | "bootm $loadaddr - $fdtaddr" |
| 909 | |
| 910 | #define CONFIG_NFSBOOTCOMMAND \ |
| 911 | "setenv bootargs root=/dev/nfs rw " \ |
| 912 | "nfsroot=$serverip:$rootpath " \ |
| 913 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 914 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 915 | "tftp $loadaddr $bootfile;" \ |
| 916 | "tftp $fdtaddr $fdtfile;" \ |
| 917 | "bootm $loadaddr - $fdtaddr" |
| 918 | |
| 919 | #define CONFIG_RAMBOOTCOMMAND \ |
| 920 | "setenv bootargs root=/dev/ram rw " \ |
| 921 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 922 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 923 | "tftp $loadaddr $bootfile;" \ |
| 924 | "tftp $fdtaddr $fdtfile;" \ |
| 925 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| 926 | |
| 927 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX |
| 928 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 929 | #include <asm/fsl_secure_boot.h> |
Aneesh Bansal | 962021a | 2016-01-22 16:37:22 +0530 | [diff] [blame] | 930 | |
Priyanka Jain | 8b1a60e | 2013-10-18 17:19:06 +0530 | [diff] [blame] | 931 | #endif /* __CONFIG_H */ |