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Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -04001/*
Hao Zhang8e697a02014-07-09 23:44:46 +03002 * Keystone : Board initialization
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -04003 *
Hao Zhang8e697a02014-07-09 23:44:46 +03004 * (C) Copyright 2014
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -04005 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
Vitaly Andrianov1ee31512016-03-11 08:23:04 -050011#include "board.h"
Hao Zhang95948202014-10-22 16:32:31 +030012#include <spl.h>
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040013#include <exports.h>
14#include <fdt_support.h>
Khoronzhuk, Ivan50df5cc2014-07-09 19:48:40 +030015#include <asm/arch/ddr3.h>
Khoronzhuk, Ivan238de852014-09-29 22:17:24 +030016#include <asm/arch/psc_defs.h>
Lokesh Vutlada18b182015-10-08 11:31:47 +053017#include <asm/arch/clock.h>
Khoronzhuk, Ivan8062b052014-06-07 05:10:49 +030018#include <asm/ti-common/ti-aemif.h>
Khoronzhuk, Ivanf2c13ba2014-09-29 22:17:22 +030019#include <asm/ti-common/keystone_net.h>
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040020
21DECLARE_GLOBAL_DATA_PTR;
22
Lokesh Vutla56c8f0a2016-04-13 09:50:59 +053023#if defined(CONFIG_TI_AEMIF)
Khoronzhuk, Ivan8062b052014-06-07 05:10:49 +030024static struct aemif_config aemif_configs[] = {
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040025 { /* CS0 */
Khoronzhuk, Ivan8062b052014-06-07 05:10:49 +030026 .mode = AEMIF_MODE_NAND,
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040027 .wr_setup = 0xf,
28 .wr_strobe = 0x3f,
29 .wr_hold = 7,
30 .rd_setup = 0xf,
31 .rd_strobe = 0x3f,
32 .rd_hold = 7,
33 .turn_around = 3,
Khoronzhuk, Ivan8062b052014-06-07 05:10:49 +030034 .width = AEMIF_WIDTH_8,
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040035 },
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040036};
Lokesh Vutla56c8f0a2016-04-13 09:50:59 +053037#endif
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040038
39int dram_init(void)
40{
Vitaly Andrianova9554d62015-02-11 14:07:58 -050041 u32 ddr3_size;
42
43 ddr3_size = ddr3_init();
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040044
45 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
46 CONFIG_MAX_RAM_BANK_SIZE);
Lokesh Vutla56c8f0a2016-04-13 09:50:59 +053047#if defined(CONFIG_TI_AEMIF)
Khoronzhuk, Ivan8062b052014-06-07 05:10:49 +030048 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
Lokesh Vutla56c8f0a2016-04-13 09:50:59 +053049#endif
50
Vitaly Andrianovbbf8ac22015-09-19 16:26:43 +053051 if (ddr3_size)
52 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
Lokesh Vutlab4b5aac2016-08-27 17:19:15 +053053 else
54 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, gd->ram_size >> 30);
55
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040056 return 0;
57}
58
Hao Zhang8e697a02014-07-09 23:44:46 +030059int board_init(void)
60{
Nishanth Menon842649d2015-07-22 18:05:43 -050061 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
Hao Zhang8e697a02014-07-09 23:44:46 +030062
63 return 0;
64}
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040065
Hao Zhang8e697a02014-07-09 23:44:46 +030066#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
Mugunthan V N33fab262016-02-02 15:51:31 +053067#ifndef CONFIG_DM_ETH
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040068int get_eth_env_param(char *env_name)
69{
70 char *env;
Hao Zhang8e697a02014-07-09 23:44:46 +030071 int res = -1;
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040072
73 env = getenv(env_name);
74 if (env)
75 res = simple_strtol(env, NULL, 0);
76
77 return res;
78}
79
80int board_eth_init(bd_t *bis)
81{
Hao Zhang8e697a02014-07-09 23:44:46 +030082 int j;
83 int res;
84 int port_num;
85 char link_type_name[32];
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040086
Vitaly Andrianovcafc8f42015-09-19 16:26:52 +053087 if (cpu_is_k2g())
88 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
89
Khoronzhuk, Ivan238de852014-09-29 22:17:24 +030090 /* By default, select PA PLL clock as PA clock source */
Vitaly Andrianovcafc8f42015-09-19 16:26:52 +053091#ifndef CONFIG_SOC_K2G
Khoronzhuk, Ivan238de852014-09-29 22:17:24 +030092 if (psc_enable_module(KS2_LPSC_PA))
93 return -1;
Vitaly Andrianovcafc8f42015-09-19 16:26:52 +053094#endif
Khoronzhuk, Ivan238de852014-09-29 22:17:24 +030095 if (psc_enable_module(KS2_LPSC_CPGMAC))
96 return -1;
97 if (psc_enable_module(KS2_LPSC_CRYPTO))
98 return -1;
99
Lokesh Vutlada18b182015-10-08 11:31:47 +0530100 if (cpu_is_k2e() || cpu_is_k2l())
101 pll_pa_clk_sel();
102
Hao Zhang8e697a02014-07-09 23:44:46 +0300103 port_num = get_num_eth_ports();
104
105 for (j = 0; j < port_num; j++) {
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400106 sprintf(link_type_name, "sgmii%d_link_type", j);
107 res = get_eth_env_param(link_type_name);
108 if (res >= 0)
109 eth_priv_cfg[j].sgmii_link_type = res;
110
111 keystone2_emac_initialize(&eth_priv_cfg[j]);
112 }
113
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400114 return 0;
115}
116#endif
Mugunthan V N33fab262016-02-02 15:51:31 +0530117#endif
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400118
Hao Zhang95948202014-10-22 16:32:31 +0300119#ifdef CONFIG_SPL_BUILD
120void spl_board_init(void)
121{
122 spl_init_keystone_plls();
123 preloader_console_init();
124}
125
126u32 spl_boot_device(void)
127{
128#if defined(CONFIG_SPL_SPI_LOAD)
129 return BOOT_DEVICE_SPI;
130#else
131 puts("Unknown boot device\n");
132 hang();
133#endif
134}
135#endif
136
Robert P. J. Day3c757002016-05-19 15:23:12 -0400137#ifdef CONFIG_OF_BOARD_SETUP
Simon Glass2aec3cc2014-10-23 18:58:47 -0600138int ft_board_setup(void *blob, bd_t *bd)
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400139{
Hao Zhang8e697a02014-07-09 23:44:46 +0300140 int lpae;
141 char *env;
142 char *endp;
143 int nbanks;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400144 u64 size[2];
Hao Zhang8e697a02014-07-09 23:44:46 +0300145 u64 start[2];
Hao Zhang8e697a02014-07-09 23:44:46 +0300146 int nodeoffset;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400147 u32 ddr3a_size;
Hao Zhang8e697a02014-07-09 23:44:46 +0300148 int unitrd_fixup = 0;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400149
150 env = getenv("mem_lpae");
151 lpae = env && simple_strtol(env, NULL, 0);
Murali Karicheri1b845322014-07-09 23:44:45 +0300152 env = getenv("uinitrd_fixup");
153 unitrd_fixup = env && simple_strtol(env, NULL, 0);
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400154
155 ddr3a_size = 0;
156 if (lpae) {
Vitaly Andrianov539de5f2016-03-04 10:36:43 -0600157 ddr3a_size = ddr3_get_size();
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400158 if ((ddr3a_size != 8) && (ddr3a_size != 4))
159 ddr3a_size = 0;
160 }
161
162 nbanks = 1;
163 start[0] = bd->bi_dram[0].start;
164 size[0] = bd->bi_dram[0].size;
165
166 /* adjust memory start address for LPAE */
167 if (lpae) {
Hao Zhang8e697a02014-07-09 23:44:46 +0300168 start[0] -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400169 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
170 }
171
172 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
173 size[1] = ((u64)ddr3a_size - 2) << 30;
174 start[1] = 0x880000000;
175 nbanks++;
176 }
177
178 /* reserve memory at start of bank */
Khoronzhuk, Ivan46e65172014-11-04 20:48:47 +0200179 env = getenv("mem_reserve_head");
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400180 if (env) {
181 start[0] += ustrtoul(env, &endp, 0);
182 size[0] -= ustrtoul(env, &endp, 0);
183 }
184
Khoronzhuk, Ivan46e65172014-11-04 20:48:47 +0200185 env = getenv("mem_reserve");
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400186 if (env)
187 size[0] -= ustrtoul(env, &endp, 0);
188
189 fdt_fixup_memory_banks(blob, start, size, nbanks);
190
191 /* Fix up the initrd */
Murali Karicheri1b845322014-07-09 23:44:45 +0300192 if (lpae && unitrd_fixup) {
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400193 int err;
Hao Zhang8e697a02014-07-09 23:44:46 +0300194 u32 *prop1, *prop2;
195 u64 initrd_start, initrd_end;
Murali Karicheri1b845322014-07-09 23:44:45 +0300196
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400197 nodeoffset = fdt_path_offset(blob, "/chosen");
198 if (nodeoffset >= 0) {
199 prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
200 "linux,initrd-start", NULL);
201 prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
202 "linux,initrd-end", NULL);
203 if (prop1 && prop2) {
204 initrd_start = __be32_to_cpu(*prop1);
Hao Zhang8e697a02014-07-09 23:44:46 +0300205 initrd_start -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400206 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
207 initrd_start = __cpu_to_be64(initrd_start);
208 initrd_end = __be32_to_cpu(*prop2);
Hao Zhang8e697a02014-07-09 23:44:46 +0300209 initrd_end -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400210 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
211 initrd_end = __cpu_to_be64(initrd_end);
212
213 err = fdt_delprop(blob, nodeoffset,
214 "linux,initrd-start");
215 if (err < 0)
216 puts("error deleting initrd-start\n");
217
218 err = fdt_delprop(blob, nodeoffset,
219 "linux,initrd-end");
220 if (err < 0)
221 puts("error deleting initrd-end\n");
222
223 err = fdt_setprop(blob, nodeoffset,
224 "linux,initrd-start",
225 &initrd_start,
226 sizeof(initrd_start));
227 if (err < 0)
228 puts("error adding initrd-start\n");
229
230 err = fdt_setprop(blob, nodeoffset,
231 "linux,initrd-end",
232 &initrd_end,
233 sizeof(initrd_end));
234 if (err < 0)
235 puts("error adding linux,initrd-end\n");
236 }
237 }
238 }
Simon Glass2aec3cc2014-10-23 18:58:47 -0600239
240 return 0;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400241}
242
243void ft_board_setup_ex(void *blob, bd_t *bd)
244{
Hao Zhang8e697a02014-07-09 23:44:46 +0300245 int lpae;
246 u64 size;
247 char *env;
248 u64 *reserve_start;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400249
250 env = getenv("mem_lpae");
251 lpae = env && simple_strtol(env, NULL, 0);
252
253 if (lpae) {
254 /*
255 * the initrd and other reserved memory areas are
256 * embedded in in the DTB itslef. fix up these addresses
257 * to 36 bit format
258 */
259 reserve_start = (u64 *)((char *)blob +
260 fdt_off_mem_rsvmap(blob));
261 while (1) {
262 *reserve_start = __cpu_to_be64(*reserve_start);
263 size = __cpu_to_be64(*(reserve_start + 1));
264 if (size) {
Hao Zhang8e697a02014-07-09 23:44:46 +0300265 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400266 *reserve_start +=
267 CONFIG_SYS_LPAE_SDRAM_BASE;
268 *reserve_start =
269 __cpu_to_be64(*reserve_start);
270 } else {
271 break;
272 }
273 reserve_start += 2;
274 }
275 }
Vitaly Andrianov19173012014-10-22 17:47:58 +0300276
277 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400278}
Robert P. J. Day3c757002016-05-19 15:23:12 -0400279#endif /* CONFIG_OF_BOARD_SETUP */