blob: 3a775be9ae9eec6128722283607de6e9b4dd820f [file] [log] [blame]
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -04001/*
2 * Copyright 2013-2015 Arcturus Networks, Inc.
3 * http://www.arcturusnetworks.com/products/ucp1020/
4 * based on board/freescale/p1_p2_rdb_pc/spl.c
5 * original copyright follows:
6 * Copyright 2013 Freescale Semiconductor, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
Simon Glassa73bda42015-11-08 23:47:45 -070012#include <console.h>
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -040013#include <ns16550.h>
14#include <malloc.h>
15#include <mmc.h>
16#include <nand.h>
17#include <i2c.h>
18#include <fsl_esdhc.h>
19#include <spi_flash.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
23static const u32 sysclk_tbl[] = {
24 66666000, 7499900, 83332500, 8999900,
25 99999000, 11111000, 12499800, 13333200
26};
27
28phys_size_t get_effective_memsize(void)
29{
30 return CONFIG_SYS_L2_SIZE;
31}
32
33void board_init_f(ulong bootflag)
34{
35 u32 plat_ratio, bus_clk;
36 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
37
38 console_init_f();
39
40 /* Set pmuxcr to allow both i2c1 and i2c2 */
41 setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
42 setbits_be32(&gur->pmuxcr,
43 in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
44
45 /* Read back the register to synchronize the write. */
46 in_be32(&gur->pmuxcr);
47
48#ifdef CONFIG_SPL_SPI_BOOT
49 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
50#endif
51
52 /* initialize selected port with appropriate baud rate */
53 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
54 plat_ratio >>= 1;
55 bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
56 gd->bus_clk = bus_clk;
57
58 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
59 bus_clk / 16 / CONFIG_BAUDRATE);
60#ifdef CONFIG_SPL_MMC_BOOT
61 puts("\nSD boot...\n");
62#elif defined(CONFIG_SPL_SPI_BOOT)
63 puts("\nSPI Flash boot...\n");
64#endif
65
66 /* copy code to RAM and jump to it - this should not return */
67 /* NOTE - code has to be copied out of NAND buffer before
68 * other blocks can be read.
69 */
70 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
71}
72
73void board_init_r(gd_t *gd, ulong dest_addr)
74{
75 /* Pointer is writable since we allocated a register for it */
76 gd = (gd_t *)CONFIG_SPL_GD_ADDR;
77 bd_t *bd;
78
79 memset(gd, 0, sizeof(gd_t));
80 bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
81 memset(bd, 0, sizeof(bd_t));
82 gd->bd = bd;
83 bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
84 bd->bi_memsize = CONFIG_SYS_L2_SIZE;
85
Simon Glass302445a2017-01-23 13:31:22 -070086 arch_cpu_init();
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -040087 get_clocks();
88 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
89 CONFIG_SPL_RELOC_MALLOC_SIZE);
90
91#ifndef CONFIG_SPL_NAND_BOOT
92 env_init();
93#endif
94#ifdef CONFIG_SPL_MMC_BOOT
95 mmc_initialize(bd);
96#endif
97 /* relocate environment function pointers etc. */
98#ifdef CONFIG_SPL_NAND_BOOT
99 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
100 (uchar *)CONFIG_ENV_ADDR);
101 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
102 gd->env_valid = 1;
103#else
104 env_relocate();
105#endif
106
107#ifdef CONFIG_SYS_I2C
108 i2c_init_all();
109#else
110 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
111#endif
112
113 gd->ram_size = initdram(0);
114#ifdef CONFIG_SPL_NAND_BOOT
115 puts("Tertiary program loader running in sram...");
116#else
117 puts("Second program loader running in sram...\n");
118#endif
119
120#ifdef CONFIG_SPL_MMC_BOOT
121 mmc_boot();
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400122#elif defined(CONFIG_SPL_NAND_BOOT)
123 nand_boot();
124#endif
125}