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Michal Simek4b066a12018-08-22 14:55:27 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2016 - 2018 Xilinx, Inc.
4 */
5
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +05306enum {
7 TCM_LOCK,
8 TCM_SPLIT,
9};
10
Siva Durga Prasad Paladuguf7a71202019-06-23 12:24:57 +053011enum pm_api_id {
12 PM_GET_API_VERSION = 1,
13 PM_SET_CONFIGURATION,
14 PM_GET_NODE_STATUS,
15 PM_GET_OPERATING_CHARACTERISTIC,
16 PM_REGISTER_NOTIFIER,
17 PM_REQUEST_SUSPEND,
18 PM_SELF_SUSPEND,
19 PM_FORCE_POWERDOWN,
20 PM_ABORT_SUSPEND,
21 PM_REQUEST_WAKEUP,
22 PM_SET_WAKEUP_SOURCE,
23 PM_SYSTEM_SHUTDOWN,
24 PM_REQUEST_NODE,
25 PM_RELEASE_NODE,
26 PM_SET_REQUIREMENT,
27 PM_SET_MAX_LATENCY,
28 PM_RESET_ASSERT,
29 PM_RESET_GET_STATUS,
30 PM_MMIO_WRITE,
31 PM_MMIO_READ,
32 PM_PM_INIT_FINALIZE,
33 PM_FPGA_LOAD,
34 PM_FPGA_GET_STATUS,
35 PM_GET_CHIPID,
36 PM_SECURE_SHA = 26,
37 PM_SECURE_RSA,
38 PM_PINCTRL_REQUEST,
39 PM_PINCTRL_RELEASE,
40 PM_PINCTRL_GET_FUNCTION,
41 PM_PINCTRL_SET_FUNCTION,
42 PM_PINCTRL_CONFIG_PARAM_GET,
43 PM_PINCTRL_CONFIG_PARAM_SET,
44 PM_IOCTL,
45 PM_QUERY_DATA,
46 PM_CLOCK_ENABLE,
47 PM_CLOCK_DISABLE,
48 PM_CLOCK_GETSTATE,
49 PM_CLOCK_SETDIVIDER,
50 PM_CLOCK_GETDIVIDER,
51 PM_CLOCK_SETRATE,
52 PM_CLOCK_GETRATE,
53 PM_CLOCK_SETPARENT,
54 PM_CLOCK_GETPARENT,
55 PM_SECURE_IMAGE,
56 PM_FPGA_READ = 46,
57 PM_SECURE_AES,
58 PM_CLOCK_PLL_GETPARAM = 49,
59 PM_REGISTER_ACCESS = 52,
60 PM_EFUSE_ACCESS,
61 PM_FEATURE_CHECK = 63,
62 PM_API_MAX,
63};
64
65#define PM_SIP_SVC 0xC2000000
66#define PAYLOAD_ARG_CNT 4U
67
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +053068void tcm_init(u8 mode);
Michal Simek21eb5cc2019-04-29 09:39:09 -070069void mem_map_fill(void);
Siva Durga Prasad Paladuguf7a71202019-06-23 12:24:57 +053070
71int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
72 u32 arg3, u32 *ret_payload);