blob: b5676578fdfdf36ea6a1e2c433502dc144c19bd7 [file] [log] [blame]
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +00001/*
2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +00005 */
6
7#include <common.h>
8#include <asm/arch/cpu.h>
9#include <asm/arch/clk.h>
10#include <asm/arch/uart.h>
11#include <asm/io.h>
12
13static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
14static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
15
16void lpc32xx_uart_init(unsigned int uart_id)
17{
18 if (uart_id < 1 || uart_id > 7)
19 return;
20
21 /* Disable loopback mode, if it is set by S1L bootloader */
22 clrbits_le32(&ctrl->loop,
23 UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
24
25 if (uart_id < 3 || uart_id > 6)
26 return;
27
28 /* Enable UART system clock */
29 setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
30
31 /* Set UART into autoclock mode */
32 clrsetbits_le32(&ctrl->clkmode,
33 UART_CLKMODE_MASK(uart_id),
34 UART_CLKMODE_AUTO(uart_id));
35
36 /* Bypass pre-divider of UART clock */
37 writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
38 &clk->u3clk + (uart_id - 3));
39}