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git01.mediatek.com / filogic / uboot / 73d044dab2b5e212b78f3973fb8bf15bec6b0136 / . / post / lib_ppc / asm.S
blob: 5e72b3418f5fcbd360292e8aa7a1144fdf194adf [file] [log] [blame]
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]1/*
2 * Copyright (C) 2002 Wolfgang Denk <wd@denx.de>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <config.h>
24
25#ifdef CONFIG_POST
26
27#include <post.h>
28#include <ppc_asm.tmpl>
29#include <ppc_defs.h>
30#include <asm/cache.h>
31
32#if CONFIG_POST & CFG_POST_CPU
33
34/* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */
35 .global cpu_post_exec_02
36cpu_post_exec_02:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]37 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]38 mflr r0
39 stwu r0, -4(r1)
40
41 subi r1, r1, 104
42 stmw r6, 0(r1)
43
44 mtlr r3
45 mr r3, r4
46 mr r4, r5
47 blrl
48
49 lmw r6, 0(r1)
50 addi r1, r1, 104
51
52 lwz r0, 0(r1)
53 addi r1, r1, 4
54 mtlr r0
55 blr
56
57/* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */
58 .global cpu_post_exec_04
59cpu_post_exec_04:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]60 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]61 mflr r0
62 stwu r0, -4(r1)
63
64 subi r1, r1, 96
65 stmw r8, 0(r1)
66
67 mtlr r3
68 mr r3, r4
69 mr r4, r5
70 mr r5, r6
71 mtxer r7
72 blrl
73
74 lmw r8, 0(r1)
75 addi r1, r1, 96
76
77 lwz r0, 0(r1)
78 addi r1, r1, 4
79 mtlr r0
80 blr
81
82/* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */
83 .global cpu_post_exec_12
84cpu_post_exec_12:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]85 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]86 mflr r0
87 stwu r0, -4(r1)
88 stwu r4, -4(r1)
89
90 mtlr r3
91 mr r3, r5
92 mr r4, r6
93 blrl
94
95 lwz r4, 0(r1)
96 stw r3, 0(r4)
97
98 lwz r0, 4(r1)
99 addi r1, r1, 8
100 mtlr r0
101 blr
102
103/* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */
104 .global cpu_post_exec_11
105cpu_post_exec_11:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]106 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]107 mflr r0
108 stwu r0, -4(r1)
109 stwu r4, -4(r1)
110
111 mtlr r3
112 mr r3, r5
113 blrl
114
115 lwz r4, 0(r1)
116 stw r3, 0(r4)
117
118 lwz r0, 4(r1)
119 addi r1, r1, 8
120 mtlr r0
121 blr
122
123/* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */
124 .global cpu_post_exec_21
125cpu_post_exec_21:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]126 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]127 mflr r0
128 stwu r0, -4(r1)
129 stwu r4, -4(r1)
130 stwu r5, -4(r1)
131
132 li r0, 0
133 mtxer r0
134 lwz r0, 0(r4)
135 mtcr r0
136
137 mtlr r3
138 mr r3, r6
139 blrl
140
141 mfcr r0
142 lwz r4, 4(r1)
143 stw r0, 0(r4)
144 lwz r4, 0(r1)
145 stw r3, 0(r4)
146
147 lwz r0, 8(r1)
148 addi r1, r1, 12
149 mtlr r0
150 blr
151
152/* void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
153 ulong op2); */
154 .global cpu_post_exec_22
155cpu_post_exec_22:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]156 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]157 mflr r0
158 stwu r0, -4(r1)
159 stwu r4, -4(r1)
160 stwu r5, -4(r1)
161
162 li r0, 0
163 mtxer r0
164 lwz r0, 0(r4)
165 mtcr r0
166
167 mtlr r3
168 mr r3, r6
169 mr r4, r7
170 blrl
171
172 mfcr r0
173 lwz r4, 4(r1)
174 stw r0, 0(r4)
175 lwz r4, 0(r1)
176 stw r3, 0(r4)
177
178 lwz r0, 8(r1)
179 addi r1, r1, 12
180 mtlr r0
181 blr
182
183/* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */
184 .global cpu_post_exec_12w
185cpu_post_exec_12w:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]186 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]187 mflr r0
188 stwu r0, -4(r1)
189 stwu r4, -4(r1)
190
191 mtlr r3
192 lwz r3, 0(r4)
193 mr r4, r5
194 mr r5, r6
195 blrl
196
197 lwz r4, 0(r1)
198 stw r3, 0(r4)
199
200 lwz r0, 4(r1)
201 addi r1, r1, 8
202 mtlr r0
203 blr
204
205/* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */
206 .global cpu_post_exec_11w
207cpu_post_exec_11w:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]208 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]209 mflr r0
210 stwu r0, -4(r1)
211 stwu r4, -4(r1)
212
213 mtlr r3
214 lwz r3, 0(r4)
215 mr r4, r5
216 blrl
217
218 lwz r4, 0(r1)
219 stw r3, 0(r4)
220
221 lwz r0, 4(r1)
222 addi r1, r1, 8
223 mtlr r0
224 blr
225
226/* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */
227 .global cpu_post_exec_22w
228cpu_post_exec_22w:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]229 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]230 mflr r0
231 stwu r0, -4(r1)
232 stwu r4, -4(r1)
233 stwu r6, -4(r1)
234
235 mtlr r3
236 lwz r3, 0(r4)
237 mr r4, r5
238 blrl
239
240 lwz r4, 4(r1)
241 stw r3, 0(r4)
242 lwz r4, 0(r1)
243 stw r5, 0(r4)
244
245 lwz r0, 8(r1)
246 addi r1, r1, 12
247 mtlr r0
248 blr
249
250/* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */
251 .global cpu_post_exec_21w
252cpu_post_exec_21w:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]253 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]254 mflr r0
255 stwu r0, -4(r1)
256 stwu r4, -4(r1)
257 stwu r5, -4(r1)
258
259 mtlr r3
260 lwz r3, 0(r4)
261 blrl
262
263 lwz r5, 4(r1)
264 stw r3, 0(r5)
265 lwz r5, 0(r1)
266 stw r4, 0(r5)
267
268 lwz r0, 8(r1)
269 addi r1, r1, 12
270 mtlr r0
271 blr
272
273/* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */
274 .global cpu_post_exec_21x
275cpu_post_exec_21x:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]276 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]277 mflr r0
278 stwu r0, -4(r1)
279 stwu r4, -4(r1)
280 stwu r5, -4(r1)
281
282 mtlr r3
283 mr r3, r6
284 blrl
285
286 lwz r5, 4(r1)
287 stw r3, 0(r5)
288 lwz r5, 0(r1)
289 stw r4, 0(r5)
290
291 lwz r0, 8(r1)
292 addi r1, r1, 12
293 mtlr r0
294 blr
295
296/* void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump,
297 ulong cr); */
298 .global cpu_post_exec_31
299cpu_post_exec_31:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]300 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]301 mflr r0
302 stwu r0, -4(r1)
303 stwu r4, -4(r1)
304 stwu r5, -4(r1)
305 stwu r6, -4(r1)
306
307 mtlr r3
308 lwz r3, 0(r4)
309 lwz r4, 0(r5)
310 mr r6, r7
311 blrl
312
313 lwz r7, 8(r1)
314 stw r3, 0(r7)
315 lwz r7, 4(r1)
316 stw r4, 0(r7)
317 lwz r7, 0(r1)
318 stw r5, 0(r7)
319
320 lwz r0, 12(r1)
321 addi r1, r1, 16
322 mtlr r0
323 blr
324
325/* int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); */
326 .global cpu_post_complex_1_asm
327cpu_post_complex_1_asm:
328 li r9,0
329 cmpw r9,r7
330 bge cpu_post_complex_1_done
331 mtctr r7
332cpu_post_complex_1_loop:
333 mullw r0,r3,r4
334 subf r0,r5,r0
335 divw r0,r0,r6
336 add r9,r9,r0
337 bdnz cpu_post_complex_1_loop
338cpu_post_complex_1_done:
339 mr r3,r9
340 blr
341
342/* int cpu_post_complex_2_asm (int x, int n); */
343 .global cpu_post_complex_2_asm
344cpu_post_complex_2_asm:
345 mr. r0,r4
346 mtctr r0
347 mr r0,r3
348 li r3,1
349 li r4,1
350 blelr
351cpu_post_complex_2_loop:
352 mullw r3,r3,r0
353 add r3,r3,r4
354 bdnz cpu_post_complex_2_loop
355blr
356
357#endif
358#endif