Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2009 |
| 3 | * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> |
| 4 | * |
Stefan Roese | 7618ad0 | 2015-08-18 09:27:17 +0200 | [diff] [blame] | 5 | * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de> |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 6 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
| 13 | /* |
| 14 | * High Level Configuration Options |
| 15 | * (easy to change) |
| 16 | */ |
| 17 | #define CONFIG_SPEAR600 /* SPEAr600 SoC */ |
| 18 | #define CONFIG_X600 /* on X600 board */ |
| 19 | |
| 20 | #include <asm/arch/hardware.h> |
| 21 | |
| 22 | /* Timer, HZ specific defines */ |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 23 | #define CONFIG_SYS_HZ_CLOCK 8300000 |
| 24 | |
| 25 | #define CONFIG_SYS_TEXT_BASE 0x00800040 |
| 26 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 |
| 27 | /* Reserve 8KiB for SPL */ |
| 28 | #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ |
| 29 | #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO |
| 30 | #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ |
| 31 | CONFIG_SYS_SPL_LEN) |
Stefan Roese | a3b2986 | 2015-08-18 09:27:20 +0200 | [diff] [blame] | 32 | #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 33 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 34 | #define CONFIG_SYS_MONITOR_LEN 0x60000 |
| 35 | |
| 36 | #define CONFIG_ENV_IS_IN_FLASH |
| 37 | |
| 38 | /* Serial Configuration (PL011) */ |
| 39 | #define CONFIG_SYS_SERIAL0 0xD0000000 |
| 40 | #define CONFIG_SYS_SERIAL1 0xD0080000 |
| 41 | #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ |
| 42 | (void *)CONFIG_SYS_SERIAL1 } |
| 43 | #define CONFIG_PL011_SERIAL |
| 44 | #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) |
| 45 | #define CONFIG_CONS_INDEX 0 |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 46 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ |
| 47 | 57600, 115200 } |
| 48 | #define CONFIG_SYS_LOADS_BAUD_CHANGE |
| 49 | |
| 50 | /* NOR FLASH config options */ |
| 51 | #define CONFIG_ST_SMI |
| 52 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 53 | #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 |
| 54 | #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } |
| 55 | #define CONFIG_SYS_MAX_FLASH_SECT 128 |
| 56 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 57 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) |
| 58 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) |
| 59 | |
| 60 | /* NAND FLASH config options */ |
| 61 | #define CONFIG_NAND_FSMC |
| 62 | #define CONFIG_SYS_NAND_SELF_INIT |
| 63 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 64 | #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE |
| 65 | #define CONFIG_MTD_ECC_SOFT |
| 66 | #define CONFIG_SYS_FSMC_NAND_8BIT |
| 67 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
Stefan Roese | 6090ad8 | 2015-09-02 11:10:59 +0200 | [diff] [blame] | 68 | #define CONFIG_NAND_ECC_BCH |
| 69 | #define CONFIG_BCH |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 70 | |
| 71 | /* UBI/UBI config options */ |
| 72 | #define CONFIG_MTD_DEVICE |
| 73 | #define CONFIG_MTD_PARTITIONS |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 74 | |
| 75 | /* Ethernet config options */ |
| 76 | #define CONFIG_MII |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 77 | #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 78 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
| 79 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
Stefan Roese | fc5ce16 | 2016-04-27 09:10:42 +0200 | [diff] [blame] | 80 | #define CONFIG_PHY_MICREL |
| 81 | #define CONFIG_PHY_MICREL_KSZ9031 |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 82 | |
| 83 | #define CONFIG_SPEAR_GPIO |
| 84 | |
| 85 | /* I2C config options */ |
Stefan Roese | ef6073e | 2014-10-28 12:12:00 +0100 | [diff] [blame] | 86 | #define CONFIG_SYS_I2C |
Alexey Brodkin | d7e3a0c | 2014-02-10 12:20:11 +0400 | [diff] [blame] | 87 | #define CONFIG_SYS_I2C_BASE 0xD0200000 |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 88 | #define CONFIG_SYS_I2C_SPEED 400000 |
| 89 | #define CONFIG_SYS_I2C_SLAVE 0x02 |
| 90 | #define CONFIG_I2C_CHIPADDRESS 0x50 |
| 91 | |
| 92 | #define CONFIG_RTC_M41T62 1 |
| 93 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
| 94 | |
| 95 | /* FPGA config options */ |
| 96 | #define CONFIG_FPGA |
| 97 | #define CONFIG_FPGA_XILINX |
| 98 | #define CONFIG_FPGA_SPARTAN3 |
| 99 | #define CONFIG_FPGA_COUNT 1 |
| 100 | |
Stefan Roese | a3b2986 | 2015-08-18 09:27:20 +0200 | [diff] [blame] | 101 | /* USB EHCI options */ |
Stefan Roese | a3b2986 | 2015-08-18 09:27:20 +0200 | [diff] [blame] | 102 | #define CONFIG_USB_EHCI_SPEAR |
Stefan Roese | a3b2986 | 2015-08-18 09:27:20 +0200 | [diff] [blame] | 103 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
| 104 | |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 105 | /* |
| 106 | * Command support defines |
| 107 | */ |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 108 | #define CONFIG_CMD_NAND |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 109 | #define CONFIG_CMD_SAVES |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 110 | |
Stefan Roese | a3b2986 | 2015-08-18 09:27:20 +0200 | [diff] [blame] | 111 | /* Filesystem support (for USB key) */ |
| 112 | #define CONFIG_SUPPORT_VFAT |
Stefan Roese | a3b2986 | 2015-08-18 09:27:20 +0200 | [diff] [blame] | 113 | |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 114 | |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 115 | /* |
| 116 | * U-Boot Environment placing definitions. |
| 117 | */ |
| 118 | #define CONFIG_ENV_SECT_SIZE 0x00010000 |
| 119 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ |
| 120 | CONFIG_SYS_MONITOR_LEN) |
| 121 | #define CONFIG_ENV_SIZE 0x02000 |
| 122 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ |
| 123 | CONFIG_ENV_SECT_SIZE) |
| 124 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
| 125 | |
| 126 | /* Miscellaneous configurable options */ |
| 127 | #define CONFIG_ARCH_CPU_INIT |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 128 | #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 |
| 129 | #define CONFIG_CMDLINE_TAG |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 130 | #define CONFIG_SETUP_MEMORY_TAGS |
| 131 | #define CONFIG_MISC_INIT_R |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 132 | #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 133 | |
| 134 | #define CONFIG_SYS_MEMTEST_START 0x00800000 |
| 135 | #define CONFIG_SYS_MEMTEST_END 0x04000000 |
Stefan Roese | a3b2986 | 2015-08-18 09:27:20 +0200 | [diff] [blame] | 136 | #define CONFIG_SYS_MALLOC_LEN (8 << 20) |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 137 | #define CONFIG_SYS_LONGHELP |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 138 | #define CONFIG_CMDLINE_EDITING |
Stefan Roese | a3b2986 | 2015-08-18 09:27:20 +0200 | [diff] [blame] | 139 | #define CONFIG_AUTO_COMPLETE |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 140 | #define CONFIG_SYS_CBSIZE 256 |
| 141 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 142 | sizeof(CONFIG_SYS_PROMPT) + 16) |
| 143 | #define CONFIG_SYS_MAXARGS 16 |
| 144 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 145 | #define CONFIG_SYS_LOAD_ADDR 0x00800000 |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 146 | |
| 147 | /* Use last 2 lwords in internal SRAM for bootcounter */ |
| 148 | #define CONFIG_BOOTCOUNT_LIMIT |
Stefan Roese | 7618ad0 | 2015-08-18 09:27:17 +0200 | [diff] [blame] | 149 | #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \ |
| 150 | CONFIG_SRAM_SIZE) |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 151 | |
| 152 | #define CONFIG_HOSTNAME x600 |
| 153 | #define CONFIG_UBI_PART ubi0 |
| 154 | #define CONFIG_UBIFS_VOLUME rootfs |
| 155 | |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 156 | #define MTDIDS_DEFAULT "nand0=nand" |
| 157 | #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" |
| 158 | |
| 159 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 160 | "u-boot_addr=1000000\0" \ |
Anatolij Gustschin | c9d1bac | 2014-10-24 20:13:51 +0200 | [diff] [blame] | 161 | "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \ |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 162 | "load=tftp ${u-boot_addr} ${u-boot}\0" \ |
Anatolij Gustschin | c9d1bac | 2014-10-24 20:13:51 +0200 | [diff] [blame] | 163 | "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ |
| 164 | " +${filesize};" \ |
| 165 | "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ |
| 166 | "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \ |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 167 | " ${filesize};" \ |
Anatolij Gustschin | c9d1bac | 2014-10-24 20:13:51 +0200 | [diff] [blame] | 168 | "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 169 | " +${filesize}\0" \ |
| 170 | "upd=run load update\0" \ |
Anatolij Gustschin | c9d1bac | 2014-10-24 20:13:51 +0200 | [diff] [blame] | 171 | "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \ |
| 172 | "part=" __stringify(CONFIG_UBI_PART) "\0" \ |
| 173 | "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 174 | "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ |
| 175 | "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ |
| 176 | " ${filesize}\0" \ |
| 177 | "upd_ubifs=run load_ubifs update_ubifs\0" \ |
| 178 | "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ |
| 179 | "ubi create ${vol} 4000000\0" \ |
| 180 | "netdev=eth0\0" \ |
| 181 | "rootpath=/opt/eldk-4.2/arm\0" \ |
| 182 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 183 | "nfsroot=${serverip}:${rootpath}\0" \ |
| 184 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| 185 | "boot_part=0\0" \ |
| 186 | "altbootcmd=if test $boot_part -eq 0;then " \ |
| 187 | "echo Switching to partition 1!;" \ |
| 188 | "setenv boot_part 1;" \ |
| 189 | "else; " \ |
| 190 | "echo Switching to partition 0!;" \ |
| 191 | "setenv boot_part 0;" \ |
| 192 | "fi;" \ |
| 193 | "saveenv;boot\0" \ |
| 194 | "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ |
| 195 | "root=ubi0:rootfs rootfstype=ubifs\0" \ |
Anatolij Gustschin | c9d1bac | 2014-10-24 20:13:51 +0200 | [diff] [blame] | 196 | "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 197 | "kernel_fs=/boot/uImage \0" \ |
| 198 | "kernel_addr=1000000\0" \ |
Anatolij Gustschin | c9d1bac | 2014-10-24 20:13:51 +0200 | [diff] [blame] | 199 | "dtb=" __stringify(CONFIG_HOSTNAME) "/" \ |
| 200 | __stringify(CONFIG_HOSTNAME) ".dtb\0" \ |
| 201 | "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \ |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 202 | "dtb_addr=1800000\0" \ |
| 203 | "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ |
| 204 | "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ |
| 205 | "addip=setenv bootargs ${bootargs} " \ |
| 206 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 207 | ":${hostname}:${netdev}:off panic=1\0" \ |
| 208 | "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ |
| 209 | "${baudrate}\0" \ |
| 210 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ |
| 211 | "net_nfs=run load_dtb load_kernel; " \ |
| 212 | "run nfsargs addip addcon addmtd addmisc;" \ |
| 213 | "bootm ${kernel_addr} - ${dtb_addr}\0" \ |
| 214 | "mtdids=" MTDIDS_DEFAULT "\0" \ |
| 215 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ |
| 216 | "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ |
| 217 | " addcon addmisc addmtd;" \ |
| 218 | "bootm ${kernel_addr} - ${dtb_addr}\0" \ |
Joe Hershberger | 108458a | 2012-11-01 16:54:18 +0000 | [diff] [blame] | 219 | "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 220 | "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ |
| 221 | "ubifsload ${dtb_addr} ${dtb_fs};\0" \ |
| 222 | "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ |
| 223 | "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ |
| 224 | "bootcmd=run nand_ubifs\0" \ |
| 225 | "\0" |
| 226 | |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 227 | /* Physical Memory Map */ |
| 228 | #define CONFIG_NR_DRAM_BANKS 1 |
| 229 | #define PHYS_SDRAM_1 0x00000000 |
| 230 | #define PHYS_SDRAM_1_MAXSIZE 0x40000000 |
| 231 | |
| 232 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
Stefan Roese | 7618ad0 | 2015-08-18 09:27:17 +0200 | [diff] [blame] | 233 | #define CONFIG_SRAM_BASE 0xd2800000 |
| 234 | /* Preserve the last 2 lwords for the boot-counter */ |
| 235 | #define CONFIG_SRAM_SIZE ((8 << 10) - 0x8) |
| 236 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE |
| 237 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 238 | |
| 239 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
| 240 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 241 | |
| 242 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 243 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| 244 | |
| 245 | /* |
| 246 | * SPL related defines |
| 247 | */ |
Stefan Roese | 7618ad0 | 2015-08-18 09:27:17 +0200 | [diff] [blame] | 248 | #define CONFIG_SPL_TEXT_BASE 0xd2800b00 |
| 249 | #define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00) |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 250 | #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" |
| 251 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" |
| 252 | |
Stefan Roese | 7618ad0 | 2015-08-18 09:27:17 +0200 | [diff] [blame] | 253 | #define CONFIG_SPL_FRAMEWORK |
Stefan Roese | 181e06b | 2012-05-30 22:59:08 +0000 | [diff] [blame] | 254 | |
| 255 | /* |
| 256 | * Please select/define only one of the following |
| 257 | * Each definition corresponds to a supported DDR chip. |
| 258 | * DDR configuration is based on the following selection |
| 259 | */ |
| 260 | #define CONFIG_DDR_MT47H64M16 1 |
| 261 | #define CONFIG_DDR_MT47H32M16 0 |
| 262 | #define CONFIG_DDR_MT47H128M8 0 |
| 263 | |
| 264 | /* |
| 265 | * Synchronous/Asynchronous operation of DDR |
| 266 | * |
| 267 | * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation |
| 268 | * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation |
| 269 | * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation |
| 270 | */ |
| 271 | #define CONFIG_DDR_2HCLK 1 |
| 272 | #define CONFIG_DDR_HCLK 0 |
| 273 | #define CONFIG_DDR_PLL2 0 |
| 274 | |
| 275 | /* |
| 276 | * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported |
| 277 | * or not. Modify/Add to only these macros to define new boot types |
| 278 | */ |
| 279 | #define USB_BOOT_SUPPORTED 0 |
| 280 | #define PCIE_BOOT_SUPPORTED 0 |
| 281 | #define SNOR_BOOT_SUPPORTED 1 |
| 282 | #define NAND_BOOT_SUPPORTED 1 |
| 283 | #define PNOR_BOOT_SUPPORTED 0 |
| 284 | #define TFTP_BOOT_SUPPORTED 0 |
| 285 | #define UART_BOOT_SUPPORTED 0 |
| 286 | #define SPI_BOOT_SUPPORTED 0 |
| 287 | #define I2C_BOOT_SUPPORTED 0 |
| 288 | #define MMC_BOOT_SUPPORTED 0 |
| 289 | |
| 290 | #endif /* __CONFIG_H */ |