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git01.mediatek.com / filogic / uboot / 7367b39d79d09a44521d311476216b0ca3c57d4e / . / board / zyxel / nsa310s / nsa310s.c
blob: cd4a7723b120e6a7dbaa00d91e8fc763e0ec4a29 [file] [log] [blame]
Tom Rini299f8f82021-07-07 22:55:41 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2015
4 * Gerald Kerma <dreagle@doukki.net>
5 * Tony Dinh <mibodhi@gmail.com>
6 */
7
8#include <common.h>
9#include <init.h>
10#include <miiphy.h>
11#include <net.h>
12#include <asm/arch/cpu.h>
13#include <asm/arch/soc.h>
14#include <asm/arch/mpp.h>
15#include <asm/global_data.h>
16#include <asm/io.h>
17#include "nsa310s.h"
18
19DECLARE_GLOBAL_DATA_PTR;
20
21int board_early_init_f(void)
22{
23 /*
24 * default gpio configuration
25 * There are maximum 64 gpios controlled through 2 sets of registers
26 * the below configuration configures mainly initial LED status
27 */
28 mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH,
29 NSA310S_OE_LOW, NSA310S_OE_HIGH);
30
31 /* (all LEDs & power off active high) */
32 /* Multi-Purpose Pins Functionality configuration */
33 static const u32 kwmpp_config[] = {
34 MPP0_NF_IO2,
35 MPP1_NF_IO3,
36 MPP2_NF_IO4,
37 MPP3_NF_IO5,
38 MPP4_NF_IO6,
39 MPP5_NF_IO7,
40 MPP6_SYSRST_OUTn,
41 MPP7_GPO,
42 MPP8_TW_SDA,
43 MPP9_TW_SCK,
44 MPP10_UART0_TXD,
45 MPP11_UART0_RXD,
46 MPP12_GPO,
47 MPP13_GPIO,
48 MPP14_GPIO,
49 MPP15_GPIO,
50 MPP16_GPIO,
51 MPP17_GPIO,
52 MPP18_NF_IO0,
53 MPP19_NF_IO1,
54 MPP20_GPIO,
55 MPP21_GPIO,
56 MPP22_GPIO,
57 MPP23_GPIO,
58 MPP24_GPIO,
59 MPP25_GPIO,
60 MPP26_GPIO,
61 MPP27_GPIO,
62 MPP28_GPIO,
63 MPP29_GPIO,
64 MPP30_GPIO,
65 MPP31_GPIO,
66 MPP32_GPIO,
67 MPP33_GPIO,
68 MPP34_GPIO,
69 MPP35_GPIO,
70 0
71 };
72 kirkwood_mpp_conf(kwmpp_config, NULL);
73 return 0;
74}
75
76int board_init(void)
77{
78 /* address of boot parameters */
79 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
80
81 return 0;
82}
83
84#ifdef CONFIG_RESET_PHY_R
85void reset_phy(void)
86{
87 u16 reg;
88 u16 phyaddr;
89 char *name = "egiga0";
90
91 if (miiphy_set_current_dev(name))
92 return;
93
94 /* read PHY dev address */
95 if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
96 printf("could not read PHY dev address\n");
97 return;
98 }
99
100 /* set RGMII delay */
101 miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
102 miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, &reg);
103 reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
104 miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
105 miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
106
107 /* reset PHY */
108 if (miiphy_reset(name, phyaddr))
109 return;
110
111 /*
112 * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
113 * and has an MCU attached to the LED[2] via tristate interrupt
114 */
115
116 /* switch to LED register page */
117 miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
118 /* read out LED polarity register */
119 miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, &reg);
120 /* clear 4, set 5 - LED2 low, tri-state */
121 reg &= ~(MV88E1318_LED2_4);
122 reg |= (MV88E1318_LED2_5);
123 /* write back LED polarity register */
124 miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);
125 /* jump back to page 0, per the PHY chip documenation. */
126 miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
127
128 /* set PHY back to auto-negotiation mode */
129 miiphy_write(name, phyaddr, 0x4, 0x1e1);
130 miiphy_write(name, phyaddr, 0x9, 0x300);
131 /* downshift */
132 miiphy_write(name, phyaddr, 0x10, 0x3860);
133 miiphy_write(name, phyaddr, 0x0, 0x9140);
134}
135#endif /* CONFIG_RESET_PHY_R */