| Jernej Skrabec | e4e040c | 2021-01-11 21:11:53 +0100 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_SUNXI=y |
| Tom Rini | a20e51f | 2021-06-28 10:17:29 -0400 | [diff] [blame] | 3 | CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-orangepi-zero2" |
| Jernej Skrabec | e4e040c | 2021-01-11 21:11:53 +0100 | [diff] [blame] | 4 | CONFIG_SPL=y |
| 5 | CONFIG_DRAM_SUN50I_H616_WRITE_LEVELING=y |
| 6 | CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION=y |
| 7 | CONFIG_DRAM_SUN50I_H616_READ_TRAINING=y |
| 8 | CONFIG_DRAM_SUN50I_H616_WRITE_TRAINING=y |
| 9 | CONFIG_MACH_SUN50I_H616=y |
| 10 | CONFIG_MMC0_CD_PIN="PF6" |
| 11 | CONFIG_R_I2C_ENABLE=y |
| Andre Przywara | 51da6fe | 2021-07-04 22:15:01 +0100 | [diff] [blame] | 12 | CONFIG_SPL_SPI_SUNXI=y |
| Jernej Skrabec | e4e040c | 2021-01-11 21:11:53 +0100 | [diff] [blame] | 13 | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
| Simon Glass | bccfc2e | 2021-07-10 21:14:36 -0600 | [diff] [blame] | 14 | CONFIG_SPL_I2C=y |
| Tom Rini | 52b2e26 | 2021-08-18 23:12:24 -0400 | [diff] [blame] | 15 | CONFIG_SPL_SYS_I2C_LEGACY=y |
| Tom Rini | 8825ec4 | 2021-08-17 17:59:47 -0400 | [diff] [blame] | 16 | CONFIG_SYS_I2C_MVTWSI=y |
| Tom Rini | a6e2923 | 2021-08-18 23:12:32 -0400 | [diff] [blame] | 17 | CONFIG_SYS_I2C_SLAVE=0x7f |
| 18 | CONFIG_SYS_I2C_SPEED=400000 |
| Andre Przywara | 87afc08 | 2022-01-11 12:46:06 +0000 | [diff] [blame] | 19 | CONFIG_SPI_FLASH_MACRONIX=y |
| Andre Przywara | 2e8edff | 2021-01-23 12:46:43 +0000 | [diff] [blame] | 20 | CONFIG_PHY_REALTEK=y |
| 21 | CONFIG_SUN8I_EMAC=y |
| Andre Przywara | 87afc08 | 2022-01-11 12:46:06 +0000 | [diff] [blame] | 22 | CONFIG_SPI=y |