| Neil Armstrong | 7c088e1 | 2018-09-05 15:56:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Copyright (c) 2016 BayLibre, SAS. |
| 4 | * Author: Neil Armstrong <narmstrong@baylibre.com> |
| 5 | * |
| 6 | * Copyright (c) 2017 Amlogic, inc. |
| 7 | * Author: Yixun Lan <yixun.lan@amlogic.com> |
| 8 | * |
| 9 | * SPDX-License-Identifier: (GPL-2.0+ OR BSD) |
| 10 | */ |
| 11 | |
| 12 | #ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H |
| 13 | #define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H |
| 14 | |
| 15 | /* RESET0 */ |
| 16 | #define RESET_HIU 0 |
| 17 | #define RESET_PCIE_A 1 |
| 18 | #define RESET_PCIE_B 2 |
| 19 | #define RESET_DDR_TOP 3 |
| 20 | /* 4 */ |
| 21 | #define RESET_VIU 5 |
| 22 | #define RESET_PCIE_PHY 6 |
| 23 | #define RESET_PCIE_APB 7 |
| 24 | /* 8 */ |
| 25 | /* 9 */ |
| 26 | #define RESET_VENC 10 |
| 27 | #define RESET_ASSIST 11 |
| 28 | /* 12 */ |
| 29 | #define RESET_VCBUS 13 |
| 30 | /* 14 */ |
| 31 | /* 15 */ |
| 32 | #define RESET_GIC 16 |
| 33 | #define RESET_CAPB3_DECODE 17 |
| 34 | /* 18-21 */ |
| 35 | #define RESET_SYS_CPU_CAPB3 22 |
| 36 | #define RESET_CBUS_CAPB3 23 |
| 37 | #define RESET_AHB_CNTL 24 |
| 38 | #define RESET_AHB_DATA 25 |
| 39 | #define RESET_VCBUS_CLK81 26 |
| 40 | #define RESET_MMC 27 |
| 41 | /* 28-31 */ |
| 42 | /* RESET1 */ |
| 43 | /* 32 */ |
| 44 | /* 33 */ |
| 45 | #define RESET_USB_OTG 34 |
| 46 | #define RESET_DDR 35 |
| 47 | #define RESET_AO_RESET 36 |
| 48 | /* 37 */ |
| 49 | #define RESET_AHB_SRAM 38 |
| 50 | /* 39 */ |
| 51 | /* 40 */ |
| 52 | #define RESET_DMA 41 |
| 53 | #define RESET_ISA 42 |
| 54 | #define RESET_ETHERNET 43 |
| 55 | /* 44 */ |
| 56 | #define RESET_SD_EMMC_B 45 |
| 57 | #define RESET_SD_EMMC_C 46 |
| 58 | #define RESET_ROM_BOOT 47 |
| 59 | #define RESET_SYS_CPU_0 48 |
| 60 | #define RESET_SYS_CPU_1 49 |
| 61 | #define RESET_SYS_CPU_2 50 |
| 62 | #define RESET_SYS_CPU_3 51 |
| 63 | #define RESET_SYS_CPU_CORE_0 52 |
| 64 | #define RESET_SYS_CPU_CORE_1 53 |
| 65 | #define RESET_SYS_CPU_CORE_2 54 |
| 66 | #define RESET_SYS_CPU_CORE_3 55 |
| 67 | #define RESET_SYS_PLL_DIV 56 |
| 68 | #define RESET_SYS_CPU_AXI 57 |
| 69 | #define RESET_SYS_CPU_L2 58 |
| 70 | #define RESET_SYS_CPU_P 59 |
| 71 | #define RESET_SYS_CPU_MBIST 60 |
| 72 | /* 61-63 */ |
| 73 | /* RESET2 */ |
| 74 | /* 64 */ |
| 75 | /* 65 */ |
| 76 | #define RESET_AUDIO 66 |
| 77 | /* 67 */ |
| 78 | #define RESET_MIPI_HOST 68 |
| 79 | #define RESET_AUDIO_LOCKER 69 |
| 80 | #define RESET_GE2D 70 |
| 81 | /* 71-76 */ |
| 82 | #define RESET_AO_CPU_RESET 77 |
| 83 | /* 78-95 */ |
| 84 | /* RESET3 */ |
| 85 | #define RESET_RING_OSCILLATOR 96 |
| 86 | /* 97-127 */ |
| 87 | /* RESET4 */ |
| 88 | /* 128 */ |
| 89 | /* 129 */ |
| 90 | #define RESET_MIPI_PHY 130 |
| 91 | /* 131-140 */ |
| 92 | #define RESET_VENCL 141 |
| 93 | #define RESET_I2C_MASTER_2 142 |
| 94 | #define RESET_I2C_MASTER_1 143 |
| 95 | /* 144-159 */ |
| 96 | /* RESET5 */ |
| 97 | /* 160-191 */ |
| 98 | /* RESET6 */ |
| 99 | #define RESET_PERIPHS_GENERAL 192 |
| 100 | #define RESET_PERIPHS_SPICC 193 |
| 101 | /* 194 */ |
| 102 | /* 195 */ |
| 103 | #define RESET_PERIPHS_I2C_MASTER_0 196 |
| 104 | /* 197-200 */ |
| 105 | #define RESET_PERIPHS_UART_0 201 |
| 106 | #define RESET_PERIPHS_UART_1 202 |
| 107 | /* 203-204 */ |
| 108 | #define RESET_PERIPHS_SPI_0 205 |
| 109 | #define RESET_PERIPHS_I2C_MASTER_3 206 |
| 110 | /* 207-223 */ |
| 111 | /* RESET7 */ |
| 112 | #define RESET_USB_DDR_0 224 |
| 113 | #define RESET_USB_DDR_1 225 |
| 114 | #define RESET_USB_DDR_2 226 |
| 115 | #define RESET_USB_DDR_3 227 |
| 116 | /* 228 */ |
| 117 | #define RESET_DEVICE_MMC_ARB 229 |
| 118 | /* 230 */ |
| 119 | #define RESET_VID_LOCK 231 |
| 120 | #define RESET_A9_DMC_PIPEL 232 |
| 121 | #define RESET_DMC_VPU_PIPEL 233 |
| 122 | /* 234-255 */ |
| 123 | |
| 124 | #endif |