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git01.mediatek.com / filogic / uboot / 733b48d802bc120534f37bf37752f068585588fe / . / include / configs / cpu9260.h
blob: de8cfb7c603535912305a591a9c380f96cfb4736 [file] [log] [blame]
Tom Rix799a05b2009-09-27 11:10:09 -0500[diff] [blame]1/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
6 *
7 * (C) Copyright 2009
8 * Eric Benard <eric@eukrea.com>
9 *
10 * Configuration settings for the Eukrea CPU9260 board.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34#define CONFIG_DISPLAY_CPUINFO 1
35
36#define AT91_MAIN_CLOCK 18432000
37#define CONFIG_SYS_HZ 1000
38
39#define CONFIG_ARM926EJS 1
40
41#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9260)
42#define CONFIG_CPU9260 1
43#elif defined(CONFIG_CPU9G20_128M) || defined(CONFIG_CPU9G20)
44#define CONFIG_CPU9G20 1
45#endif
46
47#if defined(CONFIG_CPU9G20)
48#define CONFIG_AT91SAM9G20 1
49#elif defined(CONFIG_CPU9260)
50#define CONFIG_AT91SAM9260 1
51#else
52#error "Unknown board"
53#endif
54
55#define CONFIG_ARCH_CPU_INIT
56#undef CONFIG_USE_IRQ
57
58#define CONFIG_CMDLINE_TAG 1
59#define CONFIG_SETUP_MEMORY_TAGS 1
60#define CONFIG_INITRD_TAG 1
61
62/* clocks */
63#if defined(CONFIG_CPU9G20)
64#define MASTER_PLL_DIV 0x01
65#define MASTER_PLL_MUL 0x2B
66#elif defined(CONFIG_CPU9260)
67#define MASTER_PLL_DIV 0x09
68#define MASTER_PLL_MUL 0x61
69#endif
70
71/* CKGR_MOR - enable main osc. */
72#define CONFIG_SYS_MOR_VAL \
73 (AT91_PMC_MOSCEN | \
74 (255 << 8)) /* Main Oscillator Start-up Time */
75#if defined(CONFIG_CPU9G20)
76#define CONFIG_SYS_PLLAR_VAL \
77 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
78 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
79#elif defined(CONFIG_CPU9260)
80#define CONFIG_SYS_PLLAR_VAL \
81 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
82 AT91_PMC_OUT | \
83 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
84#endif
85
86#if defined(CONFIG_CPU9G20)
87#define CONFIG_SYS_MCKR1_VAL \
88 (AT91_PMC_CSS_PLLA | \
89 AT91_PMC_PRES_1 | \
90 AT91SAM9_PMC_MDIV_6 | \
91 AT91_PMC_PDIV_2)
92#define CONFIG_SYS_MCKR2_VAL \
93 CONFIG_SYS_MCKR1_VAL
94#elif defined(CONFIG_CPU9260)
95#define CONFIG_SYS_MCKR1_VAL \
96 (AT91_PMC_CSS_SLOW | \
97 AT91_PMC_PRES_1 | \
98 AT91SAM9_PMC_MDIV_2 | \
99 AT91_PMC_PDIV_1)
100#define CONFIG_SYS_MCKR2_VAL \
101 (AT91_PMC_CSS_PLLA | \
102 AT91_PMC_PRES_1 | \
103 AT91SAM9_PMC_MDIV_2 | \
104 AT91_PMC_PDIV_1)
105#endif
106
107/* define PDC[31:16] as DATA[31:16] */
108#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
109/* no pull-up for D[31:16] */
110#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
111
112/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
113#define CONFIG_SYS_MATRIX_EBICSA_VAL \
114 (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC |\
115 AT91_MATRIX_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_VDDIOMSEL)
116
117/* SDRAM */
118/* SDRAMC_MR Mode register */
119#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
120/* SDRAMC_TR - Refresh Timer register */
121#define CONFIG_SYS_SDRC_TR_VAL1 0x287
122/* SDRAMC_CR - Configuration register*/
123#if defined(CONFIG_CPU9G20)
124#define CONFIG_SYS_SDRC_CR_VAL_64MB \
125 (AT91_SDRAMC_NC_9 | \
126 AT91_SDRAMC_NR_13 | \
127 AT91_SDRAMC_NB_4 | \
128 AT91_SDRAMC_CAS_2 | \
129 AT91_SDRAMC_DBW_32 | \
130 (2 << 8) | /* Write Recovery Delay */ \
131 (9 << 12) | /* Row Cycle Delay */ \
132 (3 << 16) | /* Row Precharge Delay */ \
133 (3 << 20) | /* Row to Column Delay */ \
134 (6 << 24) | /* Active to Precharge Delay */ \
135 (10 << 28)) /* Exit Self Refresh to Active Delay */
136
137#define CONFIG_SYS_SDRC_CR_VAL_128MB \
138 (AT91_SDRAMC_NC_10 | \
139 AT91_SDRAMC_NR_13 | \
140 AT91_SDRAMC_NB_4 | \
141 AT91_SDRAMC_CAS_2 | \
142 AT91_SDRAMC_DBW_32 | \
143 (2 << 8) | /* Write Recovery Delay */ \
144 (9 << 12) | /* Row Cycle Delay */ \
145 (3 << 16) | /* Row Precharge Delay */ \
146 (3 << 20) | /* Row to Column Delay */ \
147 (6 << 24) | /* Active to Precharge Delay */ \
148 (10 << 28)) /* Exit Self Refresh to Active Delay */
149#elif defined(CONFIG_CPU9260)
150#define CONFIG_SYS_SDRC_CR_VAL_64MB \
151 (AT91_SDRAMC_NC_9 | \
152 AT91_SDRAMC_NR_13 | \
153 AT91_SDRAMC_NB_4 | \
154 AT91_SDRAMC_CAS_2 | \
155 AT91_SDRAMC_DBW_32 | \
156 (2 << 8) | /* Write Recovery Delay */ \
157 (7 << 12) | /* Row Cycle Delay */ \
158 (2 << 16) | /* Row Precharge Delay */ \
159 (2 << 20) | /* Row to Column Delay */ \
160 (5 << 24) | /* Active to Precharge Delay */ \
161 (8 << 28)) /* Exit Self Refresh to Active Delay */
162
163#define CONFIG_SYS_SDRC_CR_VAL_128MB \
164 (AT91_SDRAMC_NC_10 | \
165 AT91_SDRAMC_NR_13 | \
166 AT91_SDRAMC_NB_4 | \
167 AT91_SDRAMC_CAS_2 | \
168 AT91_SDRAMC_DBW_32 | \
169 (2 << 8) | /* Write Recovery Delay */ \
170 (7 << 12) | /* Row Cycle Delay */ \
171 (2 << 16) | /* Row Precharge Delay */ \
172 (2 << 20) | /* Row to Column Delay */ \
173 (5 << 24) | /* Active to Precharge Delay */ \
174 (8 << 28)) /* Exit Self Refresh to Active Delay */
175#endif
176
177/* Memory Device Register -> SDRAM */
178#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
179#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
180#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
181#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
182#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
183#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
184#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
185#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
186#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
187#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
188#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
189#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
190#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
191#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
192#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
193#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
194#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
195#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
196
197/* setup SMC0, CS0 (NOR Flash) - 16-bit */
198#if defined(CONFIG_CPU9G20)
199#define CONFIG_SYS_SMC0_SETUP0_VAL \
200 (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
201 AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
202#define CONFIG_SYS_SMC0_PULSE0_VAL \
203 (AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(8) | \
204 AT91_SMC_NRDPULSE_(14) | AT91_SMC_NCS_RDPULSE_(14))
205#define CONFIG_SYS_SMC0_CYCLE0_VAL \
206 (AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(14))
207#define CONFIG_SYS_SMC0_MODE0_VAL \
208 (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
209 AT91_SMC_DBW_16 | \
210 AT91_SMC_TDFMODE | \
211 AT91_SMC_TDF_(3))
212#elif defined(CONFIG_CPU9260)
213#define CONFIG_SYS_SMC0_SETUP0_VAL \
214 (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
215 AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
216#define CONFIG_SYS_SMC0_PULSE0_VAL \
217 (AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(6) | \
218 AT91_SMC_NRDPULSE_(10) | AT91_SMC_NCS_RDPULSE_(10))
219#define CONFIG_SYS_SMC0_CYCLE0_VAL \
220 (AT91_SMC_NWECYCLE_(6) | AT91_SMC_NRDCYCLE_(10))
221#define CONFIG_SYS_SMC0_MODE0_VAL \
222 (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
223 AT91_SMC_DBW_16 | \
224 AT91_SMC_TDFMODE | \
225 AT91_SMC_TDF_(2))
226#endif
227
228/* user reset enable */
229#define CONFIG_SYS_RSTC_RMR_VAL \
230 (AT91_RSTC_KEY | \
231 AT91_RSTC_PROCRST | \
232 AT91_RSTC_RSTTYP_WAKEUP | \
233 AT91_RSTC_RSTTYP_WATCHDOG)
234
235/* Disable Watchdog */
236#define CONFIG_SYS_WDTC_WDMR_VAL \
237 (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
238 AT91_WDT_WDV | \
239 AT91_WDT_WDDIS | \
240 AT91_WDT_WDD)
241
242/*
243 * Hardware drivers
244 */
245#define CONFIG_ATMEL_USART 1
246#undef CONFIG_USART0
247#undef CONFIG_USART1
248#undef CONFIG_USART2
249#define CONFIG_USART3 1 /* USART 3 is DBGU */
250
251#define CONFIG_BOOTDELAY 3
252
253/*
254 * BOOTP options
255 */
256#define CONFIG_BOOTP_BOOTFILESIZE 1
257#define CONFIG_BOOTP_BOOTPATH 1
258#define CONFIG_BOOTP_GATEWAY 1
259#define CONFIG_BOOTP_HOSTNAME 1
260
261/*
262 * Command line configuration.
263 */
264#include <config_cmd_default.h>
265#undef CONFIG_CMD_BDI
266#undef CONFIG_CMD_IMI
267#undef CONFIG_CMD_FPGA
268#undef CONFIG_CMD_LOADS
269#undef CONFIG_CMD_IMLS
270
271#define CONFIG_CMD_PING 1
272#define CONFIG_CMD_DHCP 1
273#define CONFIG_CMD_NAND 1
274#define CONFIG_CMD_USB 1
275#define CONFIG_CMD_FAT 1
276
277/* SDRAM */
278#define CONFIG_NR_DRAM_BANKS 1
279#define PHYS_SDRAM 0x20000000
280#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
281#define PHYS_SDRAM_SIZE 0x08000000 /* 128 MB */
282#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
283#else
284#define PHYS_SDRAM_SIZE 0x04000000 /* 64 MB */
285#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
286#endif
287
288/* NAND flash */
289#define CONFIG_NAND_ATMEL 1
290#define NAND_MAX_CHIPS 1
291#define CONFIG_SYS_MAX_NAND_DEVICE 1
292#define CONFIG_SYS_NAND_BASE 0x40000000
293#define CONFIG_SYS_NAND_DBW_8 1
294#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
295#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
296#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
297#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Eric Benard2f0d10d2009-10-12 10:15:40 +0200[diff] [blame]298#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
Tom Rix799a05b2009-09-27 11:10:09 -0500[diff] [blame]299
300/* NOR flash */
301#define CONFIG_SYS_FLASH_CFI 1
302#define CONFIG_FLASH_CFI_DRIVER 1
303#define PHYS_FLASH_1 0x10000000
304#define PHYS_FLASH_2 0x12000000
305#define CONFIG_SYS_FLASH_BANKS_LIST \
306 { PHYS_FLASH_1, PHYS_FLASH_2 }
307#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
308#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
309#define CONFIG_SYS_MAX_FLASH_BANKS 2
310#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
311#define CONFIG_SYS_FLASH_EMPTY_INFO 1
312#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
313#define CONFIG_SYS_FLASH_PROTECTION 1
314#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
315
316/* Ethernet */
317#define CONFIG_MACB 1
318#define CONFIG_RMII 1
319#define CONFIG_RESET_PHY_R 1
320#define CONFIG_NET_MULTI 1
321#define CONFIG_NET_RETRY_COUNT 20
322#define CONFIG_MACB_SEARCH_PHY 1
323
324/* LEDS */
325/* Status LED */
326#define CONFIG_STATUS_LED 1 /* Status LED enabled */
327#define CONFIG_BOARD_SPECIFIC_LED 1
328#define STATUS_LED_RED 0
329#define STATUS_LED_GREEN 1
330#define STATUS_LED_YELLOW 2
331#define STATUS_LED_BLUE 3
332/* Red */
333#define STATUS_LED_BIT STATUS_LED_RED
334#define STATUS_LED_STATE STATUS_LED_OFF
335#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
336/* Green */
337#define STATUS_LED_BIT1 STATUS_LED_GREEN
338#define STATUS_LED_STATE1 STATUS_LED_OFF
339#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
340/* Yellow */
341#define STATUS_LED_BIT2 STATUS_LED_YELLOW
342#define STATUS_LED_STATE2 STATUS_LED_OFF
343#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
344/* Blue */
345#define STATUS_LED_BIT3 STATUS_LED_BLUE
346#define STATUS_LED_STATE3 STATUS_LED_ON
347#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
348/* Optional value */
349#define STATUS_LED_BOOT STATUS_LED_BIT
350
351#define CONFIG_RED_LED AT91_PIN_PC11
352#define CONFIG_GREEN_LED AT91_PIN_PC12
353#define CONFIG_YELLOW_LED AT91_PIN_PC7
354#define CONFIG_BLUE_LED AT91_PIN_PC9
355
356/* USB */
357#define CONFIG_USB_ATMEL 1
358#define CONFIG_USB_OHCI_NEW 1
359#define CONFIG_DOS_PARTITION 1
360#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
361#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
362#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
363#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
364#define CONFIG_USB_STORAGE 1
365
366#define CONFIG_SYS_LOAD_ADDR 0x21000000
367
368#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
369#define CONFIG_SYS_MEMTEST_END 0x21e00000
370
371#undef CONFIG_SYS_USE_NANDFLASH
372#define CONFIG_SYS_USE_FLASH 1
373
374#if defined(CONFIG_SYS_USE_FLASH)
375#define CONFIG_ENV_IS_IN_FLASH 1
376#define CONFIG_ENV_OFFSET 0x40000
377#define CONFIG_ENV_SECT_SIZE 0x20000
378#define CONFIG_ENV_SIZE 0x20000
379#define CONFIG_ENV_OVERWRITE 1
380
381#define CONFIG_BOOTCOMMAND "run flashboot"
382
383#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
384#define MTDPARTS_DEFAULT \
385 "mtdparts=physmap-flash.0:" \
386 "256k(u-boot)ro," \
387 "128k(u-boot-env)ro," \
388 "1792k(kernel)," \
389 "-(rootfs);" \
390 "atmel_nand:-(nand)"
391
392#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
393
394#if defined(CONFIG_CPU9G20)
395#define CONFIG_SYS_BASEDIR "cpu9G20"
396#elif defined(CONFIG_CPU9260)
397#define CONFIG_SYS_BASEDIR "cpu9260"
398#endif
399
400#define CONFIG_EXTRA_ENV_SETTINGS \
401 "mtdids=" MTDIDS_DEFAULT "\0" \
402 "mtdparts=" MTDPARTS_DEFAULT "\0" \
403 "partition=nand0,0\0" \
404 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
405 "ramboot=tftpboot 0x22000000 cpu9260/uImage;" \
406 "run ramargs;bootm 22000000\0" \
407 "flashboot=run ramargs;bootm 0x10060000\0" \
408 "basedir=" CONFIG_SYS_BASEDIR "\0" \
409 "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
410 "off 0x10000000 0x1003ffff;erase 0x10000000 " \
411 "0x1003ffff;cp.b 0x24000000 0x10000000 " \
412 "$(filesize)\0" \
413 "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
414 " 0x10060000 0x1021ffff;erase 0x10060000 " \
415 "0x1021ffff;cp.b 0x24000000 0x10060000 " \
416 "$(filesize)\0" \
417 "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
418 "protect off 0x10220000 0x13ffffff;erase " \
419 "0x10220000 0x13ffffff;cp.b 0x24000000 " \
420 "0x10220000 $(filesize)\0" \
421 ""
422#endif
423
424#define CONFIG_BAUDRATE 115200
425#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
426
427#if defined(CONFIG_CPU9G20)
428#define CONFIG_SYS_PROMPT "CPU9G20=> "
429#elif defined(CONFIG_CPU9260)
430#define CONFIG_SYS_PROMPT "CPU9260=> "
431#endif
432#define CONFIG_SYS_CBSIZE 256
433#define CONFIG_SYS_MAXARGS 16
434#define CONFIG_SYS_PBSIZE \
435 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
436#define CONFIG_SYS_LONGHELP 1
437#define CONFIG_CMDLINE_EDITING 1
438#define CONFIG_SILENT_CONSOLE 1
439#define CONFIG_NETCONSOLE 1
440
441/*
442 * Size of malloc() pool
443 */
444#define CONFIG_SYS_MALLOC_LEN \
445 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
446#define CONFIG_SYS_GBL_DATA_SIZE 128
447
448#define CONFIG_STACKSIZE (32 * 1024)
449
450#if defined(CONFIG_USE_IRQ)
451#error CONFIG_USE_IRQ not supported
452#endif
453
454#endif