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git01.mediatek.com / filogic / uboot / 7323ec827e800e4b7767280fa19f3d2e325c0241 / . / board / dvlhost / u-boot.lds
blob: f3591123230de5551a7cc0cc1236966631f115d0 [file] [log] [blame]
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
25OUTPUT_ARCH (arm)
26ENTRY (_start)
27SECTIONS
28{
29 . = 0x00000000;
30
31 . = ALIGN (4);
32 .text : {
Albert ARIBAUDc53687e2013-06-11 14:17:33 +0200[diff] [blame]33 *(.__image_copy_start)
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]34 arch/arm/cpu/ixp/start.o(.text*)
35 net/libnet.o(.text*)
36 board/dvlhost/libdvlhost.o(.text*)
37 arch/arm/cpu/ixp/libixp.o(.text*)
38 drivers/serial/libserial.o(.text*)
39
40 . = env_offset;
41 common/env_embedded.o(.ppcenv)
42 *(.text*)
43 }
44
45 . = ALIGN (4);
46 .rodata : {
47 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
48 }
49 . = ALIGN (4);
50 .data : {
51 *(.data*)
52 }
53 . = ALIGN (4);
54 .got : {
55 *(.got)
56 }
57 . =.;
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]58
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]59 . = ALIGN(4);
60 .u_boot_list : {
Albert ARIBAUDc24895e2013-02-25 00:59:00 +0000[diff] [blame]61 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]62 }
63
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]64 . = ALIGN (4);
Benoît Thébaudeau03bae032013-04-11 09:35:46 +0000[diff] [blame]65
Albert ARIBAUDc53687e2013-06-11 14:17:33 +0200[diff] [blame]66 .image_copy_end :
67 {
68 *(.__image_copy_end)
69 }
Benoît Thébaudeau03bae032013-04-11 09:35:46 +0000[diff] [blame]70
Albert ARIBAUDaf3ff162013-06-11 14:17:34 +0200[diff] [blame]71 .rel_dyn_start :
72 {
73 *(.__rel_dyn_start)
74 }
75
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]76 .rel.dyn : {
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]77 *(.rel*)
Albert ARIBAUDaf3ff162013-06-11 14:17:34 +0200[diff] [blame]78 }
79
80 .rel_dyn_end :
81 {
82 *(.__rel_dyn_end)
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]83 }
84
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]85 _end = .;
86
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]87/*
88 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
89 * __bss_base and __bss_limit are for linker only (overlay ordering)
90 */
91
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]92 .bss_start __rel_dyn_start (OVERLAY) : {
93 KEEP(*(.__bss_start));
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]94 __bss_base = .;
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]95 }
96
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]97 .bss __bss_base (OVERLAY) : {
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]98 *(.bss*)
99 . = ALIGN(4);
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]100 __bss_limit = .;
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]101 }
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]102 .bss_end __bss_limit (OVERLAY) : {
103 KEEP(*(.__bss_end));
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]104 }
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]105
Albert ARIBAUD16915932013-06-11 14:17:31 +0200[diff] [blame]106 /DISCARD/ : { *(.dynsym) }
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]107 /DISCARD/ : { *(.dynstr*) }
108 /DISCARD/ : { *(.dynamic*) }
109 /DISCARD/ : { *(.plt*) }
110 /DISCARD/ : { *(.interp*) }
111 /DISCARD/ : { *(.gnu*) }
112}